addr_gen.v

来自「基于 MAXII 的CPLD 对mobil dram 的读写操作」· Verilog 代码 · 共 38 行

/**********************************************************************************************************/
/*ADDRESS GENERATOR*/

/*Module to generate the inputs to the address bus of the sdram depending on the mode of operation*/
module addr_gen(clk,addr, pr_state, ba, a);
input clk;
input [23:0] addr;
input [4:0] pr_state;
output [1:0] ba;
output [12:0] a;
reg [1:0] ba;
reg [12:0]a;

parameter active_read_st = 5'b00001;
parameter read_st		 = 5'b00011;
parameter write_st		 = 5'b00100;
parameter lmr_st		 = 5'b01010;
parameter lemr_st		 = 5'b01110;
parameter active_write_st= 5'b10000;

always @ (posedge clk) begin
    if (pr_state == lmr_st)begin									     
	    ba <= addr[23:22];//2'b00;								
        a <= addr[12:0];		
    end	

 else if ((pr_state == active_read_st)||(pr_state ==active_write_st)) begin
	    ba <= addr[23:22];
	    a <= addr[12:0];
    end
    else if ((pr_state == read_st)||(pr_state==write_st)) begin
	    ba <=addr[23:22];
    	a <= {{4'b0010},{addr[21:13]}};
    end	
end	

endmodule
/********************************************END MODULE**********************************************************/