upcount_4.v

来自「基于 MAXII 的CPLD 对mobil dram 的读写操作」· Verilog 代码 · 共 24 行

/***************************************************************************************************************
*FOUR BIT UPCOUNTER
***************************************************************************************************************/

module upcount_4(clk, reset, count_en, count); 

input clk;                          //clk of the processor
input reset;                        //asychoronous reset
input count_en;                     
output [3:0] count;
reg [3:0] count;


always @ (posedge reset,posedge clk)begin
    if (reset==1)
        count=4'b0000;
    else
    if (count_en==1) 
        count= count + 4'b0001;
    end

endmodule

/**************************************** END MODULE **********************************************************/