test_mob_sdram.v

来自「基于 MAXII 的CPLD 对mobil dram 的读写操作」· Verilog 代码 · 共 104 行

/***************************************************************************************************************************************************
* Testbench for Mobile SDRAM
* March 2007
***************************************************************************************************************************************************/                          
`timescale 1 ns / 1 ns
 module test_mob_sdram;
 
  wire sd_clk, sd_cke, sd_csn, sd_casn, sd_rasn, sd_wen, ldqm, udqm; //signals of the controller
  wire [1:0] sd_ba;                                                  //bank address
  wire [12:0] sd_a;                                                  //data address
  wire [15:0] sd_data;                                               //data to be 4'b0001 and writtren

  reg[15:0] t_data;
  reg rw;
  reg clk, rst;                                                      //signals from the micro-processor
  reg [3:0] cmd;                                                     //specifications of the mode of operation
  reg [23:0] addr;                                                   //bank, row and column address combined, given by the micro-processor
  wire[1:0] sd_dqm;
  wire[15:0] data;
  bufif0 buffer16 [15:0] (data,t_data,rw);                           // data = t_data, when rw = 0                       //definations for the inout data type(data and sd_data)
 
 mobile_sdram dut(.sd_clk(sd_clk), .sd_cke(sd_cke), .sd_csn(sd_csn),
 .sd_casn(sd_casn), .sd_rasn(sd_rasn), .sd_wen(sd_wen),.ldqm(ldqm), .udqm(udqm), 
 .sd_ba(sd_ba), .sd_a(sd_a), .sd_data(sd_data),                      //port mapping of the main module
 .clk(clk), .rst(rst), .cmd(cmd), .data(data), .addr(addr));
  
  
assign sd_dqm[0] = udqm;
assign sd_dqm[1] = ldqm;

always    #5 clk = ~clk;                                              //setting the signal, clock of the controller = 100MHz

initial
begin
  clk = 0;
  addr = 24'b000000000000000000000000;
  t_data = 0;
  rw = 0;
  clk = 0; 
  rst = 0;
  cmd = 0;                                                             //specifications of the mode of operation
  addr = 0;
end

/* Initializing the input values of the controller */    
initial                                     
begin
    rst  = 1;
    #100 rst = 0;

	 cmd     = 4'b0000;                       //nop
    #10  cmd     = 4'b0101;                  //refresh
    $display ("The SDRAM goes through the refresh state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
    #20  cmd     = 4'b0100;                  //precharge
    $display ("The SDRAM goes through the precharge state %d", $time );
    
    #10  cmd     = 4'b0000;                  //nop
    #20  cmd     = 4'b0110;                  //dpd
    $display ("The SDRAM goes through the DPD state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
    #20  cmd     = 4'b1010;                  //dpd_exit
    $display ("The SDRAM comes out of the DPD state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
    #10  cmd     = 4'b0011;                  //power_down
    $display ("The SDRAM goes through the power down state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
    #10  cmd     = 4'b1011;                  //power_down_exit
    $display ("The SDRAM comes out of the power down state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
         addr    = 24'b000000000000000000110001;
    #10  cmd     = 4'b1000;                  //lmr
    $display ("The SDRAM goes through the Load Mode Reg. state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
         addr    = 24'b100000000000000000100000;
    #20  cmd     = 4'b1000;                  //lemr
    $display ("The SDRAM goes through the Extended Load Mode Reg. state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
	 addr = 24'b000000000000000000001000;
    #20  cmd     = 4'b0010;                  //write
    $display ("The SDRAM goes through the write state %d", $time);
    
    #10  cmd     = 4'b0000;                  //nop
    #120 cmd     = 4'b0001;                  //read
    $display ("The SDRAM goes through the read state %d", $time);
    
    #10 cmd      = 4'b0000;                  //nop    
    #120 cmd     = 4'b1100;                  //inhibit
    $display ("The SDRAM goes through the last inhibit state %d", $time); 
    
    #100 cmd     = 4'b0000;                  //nop   
   $stop;
end

endmodule
/******************************************** END ***********************************************************/