test_stepmot.v

基于 MAXII的CPLD对电机的操作

           end
                 
       if(t==25) begin
           if(test_phase== 4'b1101)
           $display ("Output Verified");
           else begin
           $display ("Error"); 
           $stop; end
           end
                 
       if(t==26) begin
           if(test_phase== 4'b1101)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end            
                       
       if(t==27) begin
           if(test_phase== 4'b1100)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
               
       if(t==28) begin
           if(test_phase== 4'b1100)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
               
       if(t==29) begin
           if(test_phase== 4'b1110)
           $display ("Output Verified");
           else begin
           $display ("Error"); 
           $stop; end
           end
              
       if(t==30) begin
           if(test_phase== 4'b1110)
           $display ("Output Verified");
           else begin
           $display ("Error");
           $stop; end
           end
             
       if(t==31) begin
           if(test_phase== 4'b0110)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
                    
       if(t==32) begin
           if(test_phase== 4'b0110)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
                   
       if(t==33) begin
           if(test_phase== 4'b0111)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
           
       if(t==34) begin
           if(test_phase== 4'b0111)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
          
       if(t==35) begin
           if(test_phase== 4'b0011)
           $display ("Output Verified");
           else begin 
           $display ("Error"); 
           $stop; end
           end
         
       if(t==36) begin
           if(test_phase== 4'b0011)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
         
       if(t==37) begin
           if(test_phase== 4'b0111)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
       
       if(t==38) begin
           if(test_phase== 4'b0111)
           $display ("Output Verified");
           else begin
           $display ("Error");
           $stop; end
           end
       
       if(t==39) begin
           if(test_phase== 4'b0110)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end 
     
       if(t==40) begin
           if(test_phase== 4'b0110)
           $display ("Output Verified");
           else begin 
           $display ("Error"); 
           $stop; end
           end
    
       if(t==41) begin
           if(test_phase== 4'b1110)
           $display ("Output Verified");
           else begin
           $display ("Error");
           $stop; end
           end
    
       if(t==42) begin
           if(test_phase== 4'b1110)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
     
       if(t==43) begin
           if(test_phase== 4'b1100)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
      
       if(t==44) begin
           if(test_phase== 4'b1100)
           $display ("Output Verified");
           else begin
           $display ("Error");
           $stop; end
           end
  
       if(t==45) begin
           if(test_phase== 4'b1101)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
   
       if(t==46) begin
           if(test_phase== 4'b1101)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end 
     
       if(t==47) begin
           if(test_phase== 4'b1001)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
   
       if(t==48) begin
           if(test_phase== 4'b1001)
           $display ("Output Verified");
           else begin 
           $display ("Error"); 
           $stop; end
           end
   
       if(t==49) begin
           if(test_phase== 4'b1011)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end
           end
    
       if(t==50) begin
           if(test_phase== 4'b1011)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end                
           end
   
       if(t==51) begin
           if(test_phase== 4'b0011)
           $display ("Output Verified");
           else begin 
           $display ("Error");
           $stop; end 
           end

       if(t==52) begin
           if(test_phase== 4'b0011)
           $display ("Output Verified");
           else begin
           $display ("Error");
           $stop; end                
           end
   
       if(t==53) begin
           if(test_phase== 4'b0111)
           $display ("Output Verified");
           else begin 
           $display ("Error"); 
           $stop; end                    
           end
   
       if(t==54) begin
           if(test_phase== 4'b0111)
           begin
           $display ("Output Verified");
           $display ("ALL TESTS PASSED");
           end
           else begin 
           $display ("Error");
           $stop; end
           
           $stop;         
           end
 
       end  
   end      

endmodule
 
/********************************************************************************************************************
* Module ufmclk is the module which gets the clock from the oscillator
********************************************************************************************************************/

`timescale 1 ps / 1 ps                           
//synopsys translate_on
module  ufmclk_altufm_osc_7p3
	( 
	osc,
	oscena) /* synthesis synthesis_clearbox=1 */;
	output   osc;
	input   oscena;

	wire  wire_maxii_ufm_block1_osc;

	maxii_ufm   maxii_ufm_block1
	( 
	.arclk(1'b0),
	.ardin(1'b0),
	.arshft(1'b0),
	.bgpbusy(),
	.busy(),
	.drclk(1'b0),
	.drdout(),
	.drshft(1'b0),
	.osc(wire_maxii_ufm_block1_osc),
	.oscena(oscena)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.drdin(1'b0),
	.erase(1'b0),
	.program(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.ctrl_bgpbusy(),
	.devclrn(),
	.devpor(),
	.sbdin(),
	.sbdout()
	// synopsys translate_on
	);
	defparam
		maxii_ufm_block1.address_width = 9,
		maxii_ufm_block1.osc_sim_setting = 180000,
		maxii_ufm_block1.lpm_type = "maxii_ufm";
	assign
		osc = wire_maxii_ufm_block1_osc;
endmodule //ufmclk_altufm_osc_7p3
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ufmclk (
	oscena,
	osc)/* synthsim:/testbench/t
esis synthesis_clearbox = 1 */;

	input	  oscena;
	output	  osc;

	wire  sub_wire0;
	wire  osc = sub_wire0;

	ufmclk_altufm_osc_7p3	ufmclk_altufm_osc_7p3_component (
				.oscena (oscena),
				.osc (sub_wire0));

endmodule

/***************************************************************************************************************************
* module divider divides the clock from ufmclk to produce a 
  clock suitable to drive the motor controller 
***************************************************************************************************************************/
 module divider1 (osc, clk,clk1);                 
	   input osc;
   	   output clk,clk1;
   	   reg clk,clk1;
       reg [16:0] count;
 initial
       count= 17'b00000000000000000;

 always @( posedge osc)
      begin
         count = count + 1;
         clk = count[16];
         clk1=count[15];
      end

endmodule

/********************************** END ********************************************************************************/