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📄 ds18b20读写程序.v

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                            else
                               begin
									counter_rd<=counter_rd+1'b1;
                                   rd_state<=RD_BIT7;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                           begin
                                               recv_reg<=recv_reg>>1;
                                               recv_reg[12]<=data;
                                        end
                                end
                            end
                        end                 
                     RD_BIT8:
                       begin
                           if(counter_rd==3500)
                              begin
                                 link_data<=0;
                                 rd_state<=RD_BIT9;
                                 counter_rd<=0;
                               end
                            else
                               begin
                                  counter_rd<=counter_rd+1'b1; 
                                   rd_state<=RD_BIT8;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                           begin
                                               recv_reg<=recv_reg>>1;
                                               recv_reg[12]<=data;
                                    	end
                                	end
                            end
                        end                                                   
                      RD_BIT9:
                       begin
                           if(counter_rd==3500)
                              begin
                                 link_data<=0;
                                 rd_state<=RD_BIT10;
                                 counter_rd<=0;
                               end
                            else
                               begin
                                   counter_rd<=counter_rd+1'b1;
                                   rd_state<=RD_BIT9;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                             begin
                                                      recv_reg<=recv_reg>>1;
                                                      recv_reg[12]<=data;

                                               end
                                        end
                                end
                        end


				RD_BIT10:
                       begin
                           if(counter_rd==3500)
                              begin
                                 link_data<=0;
                                 rd_state<=RD_BIT11;
                                 counter_rd<=0;
                               end
                            else
                               begin
                                   counter_rd<=counter_rd+1'b1;
                                   rd_state<=RD_BIT10;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                             begin
                                                
                                                      recv_reg<=recv_reg>>1;
                                                      recv_reg[12]<=data;
                                               end
                                        end
                                end
                        end


					RD_BIT11:
                       begin
                           if(counter_rd==3500)
                              begin
                                  counter_rd<=0;
                                 link_data<=0;
                                 rd_state<=RD_BIT12;
                               end
                            else
                               begin
                                   counter_rd<=counter_rd+1'b1;
                                   rd_state<=RD_BIT11;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                             begin
                                                      recv_reg<=recv_reg>>1;
                                                      recv_reg[12]<=data;
                                               end
                                        end
                                end
                        end
					RD_BIT12://to judge the sign of the temperature
                       begin
                           if(counter_rd==3500)
                              begin
                                  counter_rd<=0;
                                 link_data<=0;
                                 rd_state<=IDLE;
                                 ff<=1;
                               end
                            else
                               begin
                                   counter_rd<=counter_rd+1'b1;
                                   rd_state<=RD_BIT12;
                                   if(counter_rd<300)
                                      link_data<=1;
                                    else
                                       begin
                                           link_data<=0;
                                           if(counter_rd==500)
                                             begin
                                                      recv_reg<=recv_reg>>1;
                                                      recv_reg[12]<=data;
                                               end
											else	if(501<=counter_rd<=505)
														begin
															if(recv_reg[12]==1)
																begin
																	recv_reg[11:0]<=~recv_reg[11:0]+1'b1;
																	temp_sign<=1;
																end
															else
																begin
																	temp_sign<=0;
																	recv_reg[11:0]<=recv_reg[11:0];
																end
														end
                                        end
                                end
                        end
					default:
                       begin
						 ff<=0;
                        rd_state<=IDLE;
                        link_data<=0;
						counter_rd<=0;
                       end
               endcase
		end
		endtask
//-------------------------------reset task-----------------------------------------
//pull the bus to '0' for 490 us then release the bus for 490 us(whole cycle:490us*2)
//--------------------------------------------------------------------------------		
task reset;
			begin
				counter_rst<=counter_rst+1'b1;
				if(counter_rst<25000)
					begin
						link_data<=1;

					end
				else
					begin
						link_data<=0;
						if(counter_rst==50000)
							begin
								ff<=1;
								counter_rst<=0;
							end
					end
			end
	endtask
//------------------------------DELAY task----------------------------------------
//release the one wire bus for 750 ms
//--------------------------------------------------------------------------------
task delay;
		begin
			if(counter_test==37500000)
				begin
					ff<=1;
					counter_test<=0;
				end
			else
				counter_test<=counter_test+1'b1;
		end
endtask	
//-----------------------------data transfer---------------------------------------
//recv data transfer to its BCD code
//---------------------------------------------------------------------------------
	always @(posedge clk)
	begin
		if(!rst)	//initialize the data
			begin
				temp0<=4'b1111;
				temp1<=8'b11111111;
				ini_value<=4'b1111;
				decode_value<=8'b11111111;
				scan_bit<=4'b0000;
			end
		else
	
// stable the display data
		case(main_state)	
			READ_BIT:recv_reg_copy<=recv_reg_copy;
			default:recv_reg_copy<=recv_reg;
		endcase
// convert the low 4 bits of temperature to BCD code		
		case(recv_reg_copy[3:0])
   			4'b0000 : temp0<=4'b0000;//0   
  			4'b0001 : temp0<=4'b0001;//1
   			4'b0010 : temp0<=4'b0001;//1
   			4'b0011 : temp0<=4'b0010;//2
   			4'b0100 : temp0<=4'b0011;//3
   			4'b0101 : temp0<=4'b0011;//3
   			4'b0110 : temp0<=4'b0100;//4
   			4'b0111 : temp0<=4'b0100;//4
   			4'b1000 : temp0<=4'b0101;//5
   			4'b1001 : temp0<=4'b0110;//6
   			4'b1010 : temp0<=4'b0110;//6
  			4'b1011 : temp0<=4'b0111;//7
  			4'b1100 : temp0<=4'b1000;//8
  			4'b1101 : temp0<=4'b1000;//8
  			4'b1110 : temp0<=4'b1001;//9
   			4'b1111 : temp0<=4'b1001;//9
  			default : temp0<=4'b1111;
     	endcase
//convert the high 8 bits of temperature to BCD num	
		case(recv_reg_copy[11:4])
			8'b00000000 : temp1<=8'b00000000;//0
   			8'b00000001 : temp1<=8'b00000001;//1
   			8'b00000010 : temp1<=8'b00000010;//2
   			8'b00000011 : temp1<=8'b00000011;//3
   			8'b00000100 : temp1<=8'b00000100;//4
   			8'b00000101 : temp1<=8'b00000101;//5
   			8'b00000110 : temp1<=8'b00000110;//6
   			8'b00000111 : temp1<=8'b00000111;//7
   			8'b00001000 : temp1<=8'b00001000;//8
   			8'b00001001 : temp1<=8'b00001001;//9
   			8'b00001010 : temp1<=8'b00001010;//10
   			8'b00001011 : temp1<=8'b00010001;//11
   			8'b00001100 : temp1<=8'b00010010;//12
   			8'b00001101 : temp1<=8'b00010011;//13
   			8'b00001110 : temp1<=8'b00010100;//14
   			8'b00001111 : temp1<=8'b00010101;//15
   			8'b00010000 : temp1<=8'b00010110;//16
   			8'b00010001 : temp1<=8'b00010111;//17
   			8'b00010010 : temp1<=8'b00011000;//18
   			8'b00010011 : temp1<=8'b00011001;//19
  			8'b00010100 : temp1<=8'b00100000;//20
  		    8'b00010101 : temp1<=8'b00100001;//21
   			8'b00010110 : temp1<=8'b00100010;//22
  		    8'b00010111 : temp1<=8'b00100011;//23
   			8'b00011000 : temp1<=8'b00100100;//24
   			8'b00011001 : temp1<=8'b00100101;//25
   			8'b00011010 : temp1<=8'b00100110;//26
   			8'b00011011 : temp1<=8'b00100111;//27
   			8'b00011100 : temp1<=8'b00101000;//28
   			8'b00011101 : temp1<=8'b00101001;//29
   			8'b00011110 : temp1<=8'b00110000;//30
   			8'b00011111 : temp1<=8'b00110001;//31
   			8'b00100000 : temp1<=8'b00110010;//32
   			8'b00100001 : temp1<=8'b00110011;//33
   			8'b00100010 : temp1<=8'b00110100;//34
   			8'b00100011 : temp1<=8'b00110101;//35
   			8'b00100100 : temp1<=8'b00110110;//36
   			8'b00100101 : temp1<=8'b00110111;//37
   			8'b00100110 : temp1<=8'b00111000;//38
   			8'b00100111 : temp1<=8'b00111001;//39
   			8'b00101000 : temp1<=8'b01000000;//40
   			8'b00101001 : temp1<=8'b01000001;//41
   			8'b00101010 : temp1<=8'b01000010;//42
   			8'b00101011 : temp1<=8'b01000011;//43
   			8'b00101100 : temp1<=8'b01000100;//44
   			8'b00101101 : temp1<=8'b01000101;//45
   			8'b00101110 : temp1<=8'b01000110;//46
   			8'b00101111 : temp1<=8'b01000111;//47
   			8'b00110000 : temp1<=8'b01001000;//48
   			8'b00110001 : temp1<=8'b01001001;//49
   			8'b00110010 : temp1<=8'b01010000;//50
   			8'b00110011 : temp1<=8'b01010001;//51
   			8'b00110100 : temp1<=8'b01010010;//52
   			8'b00110101 : temp1<=8'b01010011;//53
   			8'b00110110 : temp1<=8'b01010100;//54
   			8'b00110111 : temp1<=8'b01010101;//55
   			default		: temp1<=8'b11111111;
		endcase
//led scan and scan_bit,data_bits select		
		case(scan_counter[16:15])
				2'b00:
					begin
							scan_bit<=4'b1000;
							decode_value[0]<=1'b1;
							if(temp_sign==1)
								ini_value<=4'b1010;//display"-℃"
							else
								ini_value<=4'b1111;//display"℃" 
					end
				2'b01:
					begin
							ini_value<=temp1[7:4];
							scan_bit<=4'b0100;
							decode_value[0]<=1'b1;
					end	
				2'b10:
					begin
							ini_value<=temp1[3:0];
							scan_bit<=4'b0010;
							decode_value[0]<=1'b0;
					end	
				2'b11:
					begin
							ini_value<=temp0[3:0];
							scan_bit<=4'b0001;
							decode_value[0]<=1'b1;
					end
				default :   scan_bit<=4'b0000;
			endcase
//led 7 segment decode			
			case(ini_value)
				4'b0000 :decode_value[7:1]<=7'b0000001;//0
				4'b0001 :decode_value[7:1]<=7'b1001111;//1
				4'b0010 :decode_value[7:1]<=7'b0010010;//2
				4'b0011 :decode_value[7:1]<=7'b0000110;//3
				4'b0100 :decode_value[7:1]<=7'b1001100;//4
				4'b0101 :decode_value[7:1]<=7'b0100100;//5
				4'b0110 :decode_value[7:1]<=7'b0100000;//6
				4'b0111 :decode_value[7:1]<=7'b0001111;//7
				4'b1000 :decode_value[7:1]<=7'b0000000;//8
				4'b1001 :decode_value[7:1]<=7'b0000100;//9
				4'b1010 :decode_value[7:1]<=7'b1111110;//-
				default :decode_value[7:1]<=7'b1111111;//no display
			endcase
	end

//--------------------------------scan clock ----------------------------------------		
//                           0.65536ms scan cycle
//---------------------------------------------------------------------------------
	always @(posedge clk )
		begin
			if(!rst)
				scan_counter<=0;
			else
				begin
					if(scan_counter==17'b11111111111111111)
						scan_counter<=17'b00000000000000000;
					else
						scan_counter<=scan_counter+1'b1;
				end
		end

endmodule

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