📄 ds18b20读写程序.v
字号:
end
end
WR_BIT4:
begin
if(send_reg[0])
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT5;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT4;
if(counter_wr<300)
link_data<=1;
else
link_data<=0;
end
end
else
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT5;
link_data<=0;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT4;
if(counter_wr<3000)
link_data<=1;
else
link_data<=0;
end
end
end
WR_BIT5:
begin
if(send_reg[0])
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT6;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT5;
if(counter_wr<300)
link_data<=1;
else
link_data<=0;
end
end
else
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT6;
link_data<=0;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT5;
if(counter_wr<3000)
link_data<=1;
else
link_data<=0;
end
end
end
WR_BIT6:
begin
if(send_reg[0])
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT7;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT6;
if(counter_wr<300)
link_data<=1;
else
link_data<=0;
end
end
else
begin
if(counter_wr==3500)
begin
counter_wr<=0;
wr_state<=WR_BIT7;
link_data<=0;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT6;
if(counter_wr<3000)
link_data<=1;
else
link_data<=0;
end
end
end
WR_BIT7:
begin
if(send_reg[0])
begin
if(counter_wr==3500)
begin
ff<=1;
counter_wr<=0;
wr_state<=WR_IDLE;
link_data<=0;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT7;
if(counter_wr<300)
link_data<=1;
else
link_data<=0;
end
end
else
begin
if(counter_wr==3500)
begin
ff<=1;
counter_wr<=0;
wr_state<=WR_IDLE;
link_data<=0;
send_reg<=send_reg>>1;
end
else
begin
counter_wr<=counter_wr+1'b1;
wr_state<=WR_BIT7;
if(counter_wr<3000)
link_data<=1;
else
link_data<=0;
end
end
end
default:
begin
wr_state<=WR_IDLE;
link_data<=0;
ff<=0;
counter_wr<=0;
end
endcase
end
endtask
//------------------------------read task----------------------------------------------
//pull '0' for 6 us then release the bus,at 10 us collect the one bit data(whole cycle:70us)
//-------------------------------------------------------------------------------------
task shift12_in;
begin
casex(rd_state)
IDLE:
begin
rd_state<=RD_BIT0;
link_data<=0;
counter_rd<=0;
end
RD_BIT0:
begin
if(counter_rd==3500)
begin
counter_rd<=0;
link_data<=0;
rd_state<=RD_BIT1;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT0;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT1:
begin
if(counter_rd==3500)
begin
counter_rd<=0;
link_data<=0;
rd_state<=RD_BIT2;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT1;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT2:
begin
if(counter_rd==3500)
begin
counter_rd<=0;
link_data<=0;
rd_state<=RD_BIT3;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT2;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT3:
begin
if(counter_rd==3500)
begin
counter_rd<=0;
link_data<=0;
rd_state<=RD_BIT4;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT3;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT4:
begin
if(counter_rd==3500)
begin
counter_rd<=0;
link_data<=0;
rd_state<=RD_BIT5;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT4;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT5:
begin
if(counter_rd==3500)
begin
link_data<=0;
rd_state<=RD_BIT6;
counter_rd<=0;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT5;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT6:
begin
if(counter_rd==3500)
begin
link_data<=0;
rd_state<=RD_BIT7;
counter_rd<=0;
end
else
begin
counter_rd<=counter_rd+1'b1;
rd_state<=RD_BIT6;
if(counter_rd<300)
link_data<=1;
else
begin
link_data<=0;
if(counter_rd==500)
begin
recv_reg<=recv_reg>>1;
recv_reg[12]<=data;
end
end
end
end
RD_BIT7:
begin
if(counter_rd==3500)
begin
link_data<=0;
rd_state<=RD_BIT8;
counter_rd<=0;
end
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