marsys.c

Lido PXA270平台开发板的最新BSP,包括源代码

	sPhysAddr.uiAddr = pMSysData->ui32PhysBase + MARATHON_REG_OFFSET;

	/* Needs to be shared because it is used by the clock gating clock in user & kernel */
	pMSysData->pvLinRegBaseAddr = HostMapPhysToLin(sPhysAddr,
												   MARATHON_REG_SIZE,
										           CACHETYPE_UNCACHED | EXTRA_CACHETYPE_SHARED);

	/* Read Marathon SOC_ID register. */
	ui32MarSocId = ReadHWReg(pMSysData->pvLinRegBaseAddr, MAR_SOC_ID);

	/* Get Marathon Revision ID (bits 31:24) */
	pMSysData->ui32MarathonRevID = (ui32MarSocId & 0xFF000000) >> 24;

	/* Enable ODFB active low power mode for revision A3 and later. */
	if (pMSysData->ui32MarathonRevID > 1)
	{
		pMSysData->bODFBPowerModeActiveLow = IMG_TRUE;
	}

	/* Override ODFB active power mode. */
	if(HostReadRegistryInt( 0, POWERVR_REG_ROOT, "ODFBPowerModeActiveLow", &ulValue ))
	{
		pMSysData->bODFBPowerModeActiveLow = ulValue ? IMG_TRUE : IMG_FALSE;
	}

	/* Map 1 page of SDRAM used for dummy read/writes to bring SDRAM out of SLEEP */
	sPhysAddr.uiAddr = pMSysData->ui32PhysBase + MARATHON_FB_OFFSET + (1*1024*1024);

	pMSysData->pui32SDRAMDummyArea = HostMapPhysToLin(sPhysAddr,HOST_PAGESIZE(), CACHETYPE_UNCACHED);
     
	/****** Work out bond options and ODFB/external split, setup memory info */

	/* Read SRAM hardwired bond option - this is the maximum size of the on die frame buffer. */
	ui32HardwiredSRAMBondStatus = ReadHWReg(pMSysData->pvLinRegBaseAddr, MAR_BOND_STAT);

	/* An override may change the size of the on die frame buffer by writing to MAR_BOND_CFG.
	The override value must be less than or equal the value of MAR_BOND_STAT. */
	if (bBondConfigOverride && (pMSysData->ui32BondConfig <= ui32HardwiredSRAMBondStatus))
	{
		WriteHWReg(pMSysData->pvLinRegBaseAddr, MAR_BOND_CFG, pMSysData->ui32BondConfig);
	}
	else
	{
		/* Use the value specified in MAR_BOND_STAT if there is no override. */
		PDUMPSCRIPT("RDW :REG_MSOC:%08X", MAR_BOND_STAT);
		pMSysData->ui32BondConfig = ui32HardwiredSRAMBondStatus;
	}

	switch(pMSysData->ui32BondConfig)
	{
		case MAR_BOND_CFG_0K:	pMSysData->ui32FBInteralSize  = 0;			break;
		case MAR_BOND_CFG_256K:	pMSysData->ui32FBInteralSize  = 256*1024;	break;
		case MAR_BOND_CFG_384K:	pMSysData->ui32FBInteralSize  = 384*1024;	break;
		case MAR_BOND_CFG_704K:	pMSysData->ui32FBInteralSize  = 704*1024;	break;
		default:				pMSysData->ui32FBInteralSize  = 0;			break;
	}

	pMSysData->ui32FBSize	= pMSysData->pMemConfig->ui32UDimmSize;

	/* Limit to the 32MB MBX visible region */
	if(pMSysData->ui32FBSize > 32*1024*1024)
	{ 
		pMSysData->ui32FBSize = 32*1024*1024;
	}
  
	/* Setup Slave Port physical base */
	if (pMSysData->bConfigSRAM)
	{
		/* SRAM writes to slave ports are enabled */

		IMG_UINT32 ui32SRAMPhysBase;

		/* Get Base Address corresponding to SRAM chip select and copy it to ui32SRAMPhysBase. */
		GetChipSelectBaseAddress(pMSysData->ui32SRAMChipSelect, &ui32SRAMPhysBase);

		/* Get Slave Port physical base address as an offset to SRAM physical base address. */
		pMSysData->ui32SPPhysBase = ui32SRAMPhysBase + MARATHON_SP_OFFSET;
	}
	else
	{
		/* SRAM writes to slave ports are not enabled */

		/* Get Slave Port physical base address as an offset to VLIO physical base address. */
		pMSysData->ui32SPPhysBase	= pMSysData->ui32PhysBase + MARATHON_SP_OFFSET;
	} 

	/************************************************************************/

	MarathonBoot();

	/* Memory is activated in sysconfig.c in response to first allocation request */


	/* Enable SOC level interrupt handling */
	SysGlobalEnableInterrupts();

	/******************************************************** HACK HACK HACK */

	/*
	 *	Turn on LED
	 */

	WriteHWReg(pMSysData->pvLinRegBaseAddr, 0x06C, 0x01); /* GPIO0 is output */
	WriteHWReg(pMSysData->pvLinRegBaseAddr, 0x070, 0x01); /* GPIO0 is set Low */ /* These turn the LED on */

	PDUMPSCRIPT("---- SysBoot fini");
	PDUMPREGMBX;

	return(PVRSRV_OK);
}									    

/*****************************************************************************
 FUNCTION	: GetChipSelectBaseAddress
    
 PURPOSE	: Get the physical base address of the specified chip select.

 PARAMETERS	: IMG_UINT32 ui32ChipSelect        : (input)  required chip select
			  IMG_UINT32* pui32PhysBaseAddress : (output) physical base address of chip select
 RETURNS	: 
*****************************************************************************/
static void GetChipSelectBaseAddress(IMG_UINT32 ui32ChipSelect, IMG_UINT32* pui32PhysBaseAddress)
{
	/* Make sure that the chip select is within the permitted range. */
	PVR_ASSERT((ui32ChipSelect >= 0));
	PVR_ASSERT((ui32ChipSelect <= 5));

	*pui32PhysBaseAddress = 0xFFFFFFFF;

	/* Get base address of Host GSB Interface */
	switch (ui32ChipSelect)
	{
		case 0:
			/* ChipSelect0 Base Address */
			*pui32PhysBaseAddress = 0x00000000;
		break;

		case 1:
			/* ChipSelect1 Base Address */
			*pui32PhysBaseAddress = 0x04000000;
		break;

		case 2:
			/* ChipSelect2 Base Address - NOTE: required base address may be 0x0A000000 (for SRAM).
			Refer to Bulverde user manual. */
			*pui32PhysBaseAddress = 0x08000000; // ?
		break;

		case 3:
			/* ChipSelect3 Base Address */
			*pui32PhysBaseAddress = 0x0C000000;
		break;

		case 4:
			/* ChipSelect4 Base Address */
			*pui32PhysBaseAddress = 0x10000000;
		break;

		case 5:
			/* ChipSelect5 Base Address */
			*pui32PhysBaseAddress = 0x14000000;
		break;

		default:
			/* Chip select number is invalid */
			PVR_ASSERT(1);
			break;
	}

	PVR_ASSERT((*pui32PhysBaseAddress != 0xFFFFFFFF));
}

/*****************************************************************************
 FUNCTION	: SysSetPixClkFrequency
    
 PURPOSE	: Called to set the pixel clock frequnecy

 PARAMETERS	: IMG_UINT32 ui32Freq
			  
 RETURNS	: Frequency set
*****************************************************************************/

DWORD SysSetPixClkFrequency(IMG_UINT32 ui32Freq)
{
	IMG_BOOL			bRet;
	PSYS_SPECIFIC_DATA	pMSysData;

	GET_MARATHON_SYS_DATA(pMSysData);

	if(ui32Freq == 0)
	{
		/* Special case - called during entry into D3 */
		pMSysData->ui32PixClk = 0;
		bRet = FALSE;
	}
	else
	{
		bRet = SetPLL(1, ui32Freq, &pMSysData->ui32PixClk);

		PDUMPSCRIPT("---- SysSetPixClkFrequency start");
		PDUMPREGTAG(PDUMPTAGS_REG_MSOC, 0);

		if(bRet)
		{
			WriteHWReg(pMSysData->pvLinRegBaseAddr, MAR_PIXCLK_SELECT, MAR_PIXCLK_SELECT_PLL1);
		}
		else
		{
			WriteHWReg(pMSysData->pvLinRegBaseAddr, MAR_PIXCLK_SELECT, MAR_PIXCLK_SELECT_REFCLK);
		}
			HostWaitus(250); // HACK

//		ChangeSYSCLK(pMSysData->ui32SysClk);
	}
	PDUMPSCRIPT("---- SysSetPixClkFrequency fini");
	PDUMPREGMBX;

	return(bRet);
}

static void ProgramLCDConfig()
{
	IMG_UINT32			ui32Val;
	PSYS_SPECIFIC_DATA	pMSysData;

	GET_MARATHON_SYS_DATA(pMSysData);

	switch(pMSysData->sLCDState.eGIBFormat)
	{
		case SYS_HOST_LCD_555:
			ui32Val = MAR_LCD_GIB_FORMAT_555;
			break;
		case SYS_HOST_LCD_556:
			ui32Val = MAR_LCD_GIB_FORMAT_556;
			break;
		case SYS_HOST_LCD_565:
			ui32Val = MAR_LCD_GIB_FORMAT_565;
			break;
		case SYS_HOST_LCD_655:
			ui32Val = MAR_LCD_GIB_FORMAT_655;
			break;
		case SYS_HOST_LCD_665:
			ui32Val = MAR_LCD_GIB_FORMAT_665;
			break;
		case SYS_HOST_LCD_666:
			ui32Val = MAR_LCD_GIB_FORMAT_666;
			break;
		default:
			ui32Val = 0;
			break;
	}

	ui32Val = ui32Val << MAR_LCD_GIB_FORMAT_SHIFT;

	if (pMSysData->sLCDState.sLCD1Config.eDENPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD1DEN_POL;
	if (pMSysData->sLCDState.sLCD2Config.eDENPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD2DEN_POL;

	if (pMSysData->sLCDState.sLCD1Config.eFCLKPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD1FCLK_POL;
	if (pMSysData->sLCDState.sLCD2Config.eFCLKPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD2FCLK_POL;

	if (pMSysData->sLCDState.sLCD1Config.eLCLKPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD1LCLK_POL;
	if (pMSysData->sLCDState.sLCD2Config.eDENPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD2LCLK_POL;

	if (pMSysData->sLCDState.sLCD1Config.eDataPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD1_D_POL;
	if (pMSysData->sLCDState.sLCD2Config.eDataPolarity == SYS_RISING)
		ui32Val |= MAR_LCD_LCD2_D_POL;

	if (pMSysData->sLCDState.sLCD1Config.bActive)
		ui32Val |= MAR_LCD_LCD1_TS;
	// if (pMSysData->sLCDState.sLCD2Config.bActive)	//SG2-G For Two displays are turned on 
		ui32Val |= MAR_LCD_LCD2_TS;

	if (pMSysData->sLCDState.sLCD1Config.eDataStrength == SYS_6MA_10MA)
		ui32Val |= MAR_LCD_LCD1D_DS;
	if (pMSysData->sLCDState.sLCD2Config.eDataStrength == SYS_6MA_10MA)
		ui32Val |= MAR_LCD_LCD2D_DS;

	if (pMSysData->sLCDState.sLCD1Config.eClockStrength == SYS_6MA_10MA)
		ui32Val |= MAR_LCD_LCD1C_DS;
	if (pMSysData->sLCDState.sLCD2Config.eClockStrength == SYS_6MA_10MA)
		ui32Val |= MAR_LCD_LCD2C_DS;

	if (pMSysData->sLCDState.sLCD1Config.eSource == SYS_SOURCE_HOST)
		ui32Val |= MAR_LCD_LCD1_IS_GIB;
	if (pMSysData->sLCDState.sLCD2Config.eSource == SYS_SOURCE_HOST)
		ui32Val |= MAR_LCD_LCD2_IS_GIB;

	PDUMPSCRIPT("---- ProgramLCDConfig start");

	WriteHWReg(pMSysData->pvLinRegBaseAddr, MAR_LCD_CONFIG, ui32Val);

	PDUMPSCRIPT("---- ProgramLCDConfig fini");
}

void SysConfigLCD(IMG_UINT32 ui32LCD, PSYS_LCD_CONFIG psConfig)
{
	PSYS_SPECIFIC_DATA	pMSysData;

	GET_MARATHON_SYS_DATA(pMSysData);

	PDUMPSCRIPT("---- SysConfigLCD start");
	PDUMPREGTAG(PDUMPTAGS_REG_MSOC, 0);

	switch (ui32LCD)
	{
		case 1: pMSysData->sLCDState.sLCD1Config = *psConfig; break;
		case 2: pMSysData->sLCDState.sLCD2Config = *psConfig; break;

		default: break;
	}

	ProgramLCDConfig();

	PDUMPSCRIPT("---- SysConfigLCD fini");
	PDUMPREGMBX;
}

void SysConfigHostLCDFormat(SYS_GIB_FORMAT eFormat)
{
	PSYS_SPECIFIC_DATA	pMSysData;

	GET_MARATHON_SYS_DATA(pMSysData);

	PDUMPSCRIPT("---- SysConfigHostLCDFormat start");
	PDUMPREGTAG(PDUMPTAGS_REG_MSOC, 0);

	pMSysData->sLCDState.eGIBFormat = eFormat;
	ProgramLCDConfig();

	PDUMPSCRIPT("---- SysConfigHostLCDFormat fini");
	PDUMPREGMBX;
}

/*****************************************************************************
 FUNCTION	: SysSRAMOverflowDetected()
    
 PURPOSE	: 

 PARAMETERS	:  
			  
 RETURNS	: 
*****************************************************************************/

#define SINT_GSB_SPOVERFLOW	(0x1 << 3)

IMG_BOOL SysSRAMOverflowDetected()
{
	IMG_UINT32			ui32SInt;
	PSYS_SPECIFIC_DATA	pMSysData;

	GET_MARATHON_SYS_DATA(pMSysData);

	ui32SInt = ReadHWReg(pMSysData->pvLinRegBaseAddr, MAR_SINT_STAT);

	WriteHWReg(pMSysData->pvLinRegBaseAddr, MAR_SINT_CLEAR, SINT_GSB_SPOVERFLOW);

	return(ui32SInt & SINT_GSB_SPOVERFLOW);
}


/*****************************************************************************/
/****************************** Debug functions ******************************/
/*****************************************************************************/

#ifdef LOCAL_MEMORY_SELF_REFRESH_TESTING
	#ifdef DEBUG
		#define OLD_DEBUG DEBUG
	#endif // DEBUG
	#define DEBUG 1
#endif // LOCAL_MEMORY_SELF_REFRESH_TESTING
#ifdef DEBUG

#define BASEBOARD_REG_MAP_SIZE			(4*1024)	//4K
#define BASEBOARD_REG_PHYSICAL_ADDR		(0x08000000)	
#define LED_DATA		0x10
#define LED_CTRL		0x40
#define USER_SWITCHES	0x60

static volatile PDWORD	g_pdwBaseRegs=0;

/*****************************************************************************
 FUNCTION	: SysWriteLEDData
    
 PURPOSE	: Output Data on the Lubbock and Mainstone LED displays

 PARAMETERS	: DWORD dwData   - The Value to display	 
			  
 RETURNS	: 
*****************************************************************************/

void SysWriteLEDData(IMG_UINT32 ui32Data)
{
	IMG_UINT32	ui32Ctrl;
	
	if(!g_pdwBaseRegs)
	{
		IMG_CPU_PHYADDR sPhysAddr;

		sPhysAddr.uiAddr = BASEBOARD_REG_PHYSICAL_ADDR;

		g_pdwBaseRegs = (PDWORD) HostMapPhysToLin(sPhysAddr,
												  BASEBOARD_REG_MAP_SIZE,
												  CACHETYPE_UNCACHED);
	}

	ui32Ctrl = g_pdwBaseRegs[LED_CTRL / sizeof(DWORD)];

	g_pdwBaseRegs[LED_CTRL / sizeof(DWORD)]=(ui32Ctrl&0xffff00ff);
	g_pdwBaseRegs[LED_DATA / sizeof(DWORD)]=ui32Data;

	return;
}

/*****************************************************************************
 FUNCTION	: SysWriteLEDBits
    
 PURPOSE	: Set the LEDS D21 to D28 

 PARAMETERS	: BYTE byData
			  
 RETURNS	: 
*****************************************************************************/

void SysWriteLEDBits(IMG_UINT8 ui8Data)
{
	IMG_UINT32	ui32Ctrl;
	
	if(!g_pdwBaseRegs)
	{
		IMG_CPU_PHYADDR sPhysAddr;

		sPhysAddr.uiAddr = BASEBOARD_REG_PHYSICAL_ADDR;

		g_pdwBaseRegs = (PDWORD) HostMapPhysToLin(sPhysAddr,
												  BASEBOARD_REG_MAP_SIZE,
												  CACHETYPE_UNCACHED);
	}

	ui32Ctrl = g_pdwBaseRegs[LED_CTRL / sizeof(DWORD)];
	ui32Ctrl = (ui32Ctrl & 0xffffff00) | (0xff & (~ui8Data));

	g_pdwBaseRegs[LED_CTRL / sizeof(DWORD)] = ui32Ctrl;

	return;
	
}

/*****************************************************************************
 FUNCTION	: SysReadUserSwitches
    
 PURPOSE	: Read the State of User swithces S17 to S22 

 PARAMETERS	: 
			  
 RETURNS	: 	The value of the switches
*****************************************************************************/

IMG_UINT8 SysReadUserSwitches(void)
{
	IMG_UINT32	ui32Data;

	if(!g_pdwBaseRegs)
	{
		IMG_CPU_PHYADDR sPhysAddr;

		sPhysAddr.uiAddr = BASEBOARD_REG_PHYSICAL_ADDR;

		g_pdwBaseRegs = (PDWORD) HostMapPhysToLin(sPhysAddr,
												  BASEBOARD_REG_MAP_SIZE,
												  CACHETYPE_UNCACHED);
	}

	ui32Data = g_pdwBaseRegs[USER_SWITCHES / sizeof(DWORD)];

	return (IMG_UINT8)((ui32Data >> 10) & 0x3f);
}

#endif /* #ifdef DEBUG */
#ifdef LOCAL_MEMORY_SELF_REFRESH_TESTING
	#ifdef OLD_DEBUG
		#undef DEBUG
		#define DEBUG OLD_DEBUG 
	#endif // OLD_DEBUG
#endif // LOCAL_MEMORY_SELF_REFRESH_TESTING


#endif /* #ifdef SUPPORT_MARATHON_DEVICE */
/*--------------------------------- end of file ------------------------------*/