📄 marathon.h
字号:
/*******************************************************************************
* Name : marathon.h
* Title : Marathon hardware defines
* Author : Tim Rowley
* Created : 28th February 2003
*
* Copyright : 2003 by Imagination Technologies Limited.
* All rights reserved. No part of this software, either
* material or conceptual may be copied or distributed,
* transmitted, transcribed, stored in a retrieval system
* or translated into any human or computer language in any
* form by any means, electronic, mechanical, manual or
* other-wise, or disclosed to third parties without the
* express written permission of Imagination Technologies
* Limited, Unit 8, HomePark Industrial Estate,
* King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description : Marathon hardware defines
*
* Platform : Generic
*
* Modifications:-
* $Log: marathon.h $
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*******************************************************************************/
/*
Notes : based on version 1.16 from MKS. No modifications required for initial
port
*/
#ifndef MARATHON_H
#define MARATHON_H
// Special sleep feature
#define SLEEP_MARATHON_OFF 1
#ifdef SLEEP_MARATHON_OFF
#if !SLEEP_MARATHON_OFF
#undef SLEEP_MARATHON_OFF
#endif
#endif
// Display refresh feature
#define LOCAL_MEMORY_SELF_REFRESH 1
#define LOCAL_MEMORY_SELF_REFRESH_TESTING 0
#define DEFAULT_LOCAL_MEMORY_TIMEOUT 10000
#define LOCAL_MEMORY_MINIMUM_DELAY 10 // 10 milliseconds to allow HW to flush
#ifdef LOCAL_MEMORY_SELF_REFRESH
#if !LOCAL_MEMORY_SELF_REFRESH
#undef LOCAL_MEMORY_SELF_REFRESH
#endif
#endif
#define REDUCE_FREQ_IN_DISP_REFRESH 0
#ifdef REDUCE_FREQ_IN_DISP_REFRESH
#if !REDUCE_FREQ_IN_DISP_REFRESH
#undef REDUCE_FREQ_IN_DISP_REFRESH
#endif
#endif
//#define MARATHON_FPGA
#define BULVERDE_B_STEPPING /* Needed for post-B rev XScales */
#ifdef MARATHON_FPGA
#define MAR_REFCLK_FREQ 12000000
#else
#define MAR_REFCLK_FREQ 13000000
#endif
#define MAR_MAXFREQ_MBX 75000000
#define MAR_MAXFREQ_M24VA 75000000
#define MAR_ODFB_FREQ_THRESHOLD 66000000
#define MAR_PLL_MIN_M 1
#define MAR_PLL_MAX_M 63
#define MAR_PLL_MIN_N 1
#define MAR_PLL_MAX_N 7
#define MAR_PLL_MIN_P 0
#define MAR_PLL_MAX_P 7
#define MAR_PLL_MIN_VCO 47000000
#define MAR_PLL_MAX_VCO 168000000
#define MAR_PLL_MIN_POSTDIV 1
#define MAR_PLL_MAX_POSTDIV 511
#define TREFCLK 77
#define PWM_MAX_PRESCALE 64
#define PWM_MAX_PCONTROL 1024
#define PWM_MAX_PERIOD TREFCLK*PWM_MAX_PRESCALE*PWM_MAX_PCONTROL
#define SYSCLK_BOOT_VAL 133000000
#define PIXCLK_BOOT_VAL 13000000
#define MAR_SYS_CONFIG 0x0000
#define MAR_SYS_TIMEOUT_EN (1<<24)
#define MAR_SYS_RESET 0x0010
#define MAR_INT_MINPW 0x0014
#define MAR_MINT_ENABLE 0x0018
#define MAR_MINT_STAT 0x001C
#define MAR_SINT_ENABLE 0x0020
#define MAR_SINT_BIT_MASTER (1<<15)
#define MAR_SINT_BIT_CLKSW (1<<4)
#define MAR_SINT_BIT_SP_OVERFLOW (1<<3)
#define MAR_SINT_BIT_SP_ADDRESS (1<<2)
#define MAR_SINT_BIT_MC_PROTECT (1<<1)
#define MAR_SINT_BIT_GSB_TIMEOUT (1<<0)
#define MAR_SINT_ALL_BITS (0x800F)
#define MAR_SINT_STAT 0x0024
#define MAR_SINT_CLEAR 0x0028
#define MAR_SYSCLK_SELECT 0x002C
#define MAR_SYSCLK_SELECT_REFCLK 0
#define MAR_SYSCLK_SELECT_PLL0 2
#define MAR_SYSCLK_SELECT_PLL1 1
#define MAR_PIXCLK_SELECT 0x0030
#define MAR_PIXCLK_SELECT_REFCLK 0
#define MAR_PIXCLK_SELECT_PLL1 1
#define MAR_PLL0_CTL 0x0038
#define MAR_PLL1_CTL 0x003C
#define MAR_PLL_STAT 0x0040
#define MAR_PLL_STAT_SYS_LOCKED 0x4
#define MAR_PLL_STAT_PIX_LOCKED 0x1
#define MAR_VIDCLK_CONFIG 0x0044
#define MAR_VIDCLK_CONFIG_ON 1
#define MAR_VIDCLK_CONFIG_OFF 0
#define MAR_PIXCLK_CONFIG 0x0048
#define MAR_PIXCLK_CONFIG_ON 1
#define MAR_PIXCLK_CONFIG_OFF 0
#define MAR_MEMCLK_CONFIG 0x004C
#define MAR_MEMCLK_CONFIG_ON 1
#define MAR_MEMCLK_CONFIG_OFF 0
#define MAR_M24CLK_CONFIG 0x0050
#define MAR_M24CLK_CONFIG_ON 1
#define MAR_M24CLK_CONFIG_OFF 0
#define MAR_MBXCLK_CONFIG 0x0054
#define MAR_MBXCLK_CONFIG_ALL 2
#define MAR_MBXCLK_CONFIG_2D 1
#define MAR_MBXCLK_CONFIG_OFF 0
#define MAR_SDCLK_CONFIG 0x0058
#define MAR_SDCLK_CONFIG_ON 1
#define MAR_SDCLK_CONFIG_OFF 0
#define MAR_PIXCLK_DIV 0x005C
#define MAR_LCD_CONFIG 0x0060
#define MAR_LCD_GIB_FORMAT_SHIFT 28
#define MAR_LCD_GIB_FORMAT_555 0
#define MAR_LCD_GIB_FORMAT_556 1
#define MAR_LCD_GIB_FORMAT_565 2
#define MAR_LCD_GIB_FORMAT_655 3
#define MAR_LCD_GIB_FORMAT_665 4
#define MAR_LCD_GIB_FORMAT_666 5
#define MAR_LCD_LCD1DEN_POL (1 << 27)
#define MAR_LCD_LCD1FCLK_POL (1 << 26)
#define MAR_LCD_LCD1LCLK_POL (1 << 25)
#define MAR_LCD_LCD1_D_POL (1 << 24)
#define MAR_LCD_LCD2DEN_POL (1 << 23)
#define MAR_LCD_LCD2FCLK_POL (1 << 22)
#define MAR_LCD_LCD2LCLK_POL (1 << 21)
#define MAR_LCD_LCD2_D_POL (1 << 20)
#define MAR_LCD_LCD1_TS (1 << 19)
#define MAR_LCD_LCD1D_DS (1 << 18)
#define MAR_LCD_LCD1C_DS (1 << 17)
#define MAR_LCD_LCD1_IS_GIB (1 << 16)
#define MAR_LCD_LCD2_TS (1 << 3)
#define MAR_LCD_LCD2D_DS (1 << 2)
#define MAR_LCD_LCD2C_DS (1 << 1)
#define MAR_LCD_LCD2_IS_GIB (1 << 0)
#define MAR_ODFB_POWERMODE 0x0064
#define MAR_ODFB_POWERMODE_SLOW_HIGH 0<<2
#define MAR_ODFB_POWERMODE_SLOW_LOW 1<<2
#define MAR_ODFB_POWERMODE_MODE_ACTIVE 0
#define MAR_ODFB_POWERMODE_MODE_ACTIVE_LOW 1
#define MAR_ODFB_POWERMODE_MODE_SLEEP 2
#define MAR_ODFB_POWERMODE_MODE_SHUTDOWN 3
#define MAR_MBX_RESET 0x00C0
#define MAR_PDP_RESET 0x00C4
#define MAR_M24VA_RESET 0x00C8
#define MAR_POST_TEST0 0x104
#define MAR_POST_TEST1 0x108
#define MAR_PWM_CFG 0x0204
#define MAR_PWM_CR0 0x0210
#define MAR_PWM_DCR0 0x0214
#define MAR_PWM_PCR0 0x0218
#define MAR_PWM_CR1 0x0220
#define MAR_PWM_DCR1 0x0224
#define MAR_PWM_PCR1 0x0228
#define MAR_BOND_STAT 0x0300
#define MAR_BOND_CFG 0x0304
#define MAR_SOC_ID 0x0FF0
#define MAR_BOND_CFG_0K 0x0
#define MAR_BOND_CFG_256K 0x1
#define MAR_BOND_CFG_384K 0x2
#define MAR_BOND_CFG_704K 0x3
#define MC_POWERDOWN_CONTROL 0x1008
#define MC_POWERDOWN_CONTROL_ACTIVE 0
#define MC_POWERDOWN_CONTROL_SELF_REFRESH 1
#define MC_POWERDOWN_CONTROL_SHUTDOWN 3
#define MC_CONFIG 0x1004
#define MC_CONFIG_LMC_DS 0x20
#define MC_CONFIG_LMD_DS 0x10
#define MC_CONFIG_LMA_DS 0x8
#define MC_CONFIG_LMC_TS 0x4
#define MC_CONFIG_LMD_TS 0x2
#define MC_CONFIG_LMA_TS 0x1
#define MC_TYPE 0x1014
#define MC_TYPE_CAS_LATENCY_SHIFT 10
#define MC_TYPE_BANK_SIZE_SHIFT 8
#define MC_TYPE_ROW_SIZE_SHIFT 4
#define MC_TYPE_COL_SIZE_SHIFT 0
#define MC_TIMING 0x1018
#define MC_TIMING_TRAS_SHIFT 16
#define MC_TIMING_TRP_SHIFT 12
#define MC_TIMING_TRCD_SHIFT 8
#define MC_TIMING_TRC_SHIFT 4
#define MC_TIMING_TDPL_SHIFT 0
#define MC_REFRESH 0x101c
#define MAR_GFXINT_ENABLE 0x4130
#define MAR_VAINT_MASK 0x3084
/***************************************************** Global data structure */
typedef struct _LCD_SWITCH_STATE_
{
/* LCD switch state */
SYS_GIB_FORMAT eGIBFormat;
SYS_LCD_CONFIG sLCD1Config;
SYS_LCD_CONFIG sLCD2Config;
} LCD_SWITCH_STATE, *PLCD_SWITCH_STATE;
#ifdef SLEEP_MARATHON_OFF
// Registers to be saved and restored upon sleep
typedef struct
{
// Clock registers
IMG_UINT32 ui32ClkMBX; /* MAR_MBXCLK_CONFIG - 0054 */
IMG_UINT32 ui32ClkM24VA; /* MAR_M24CLK_CONFIG - 0050 */
IMG_UINT32 ui32ClkPDP_GP; /* MAR_PIXCLK_CONFIG - 0048 */
IMG_UINT32 ui32ClkPDP_OP; /* MAR_VIDCLK_CONFIG - 0044 */
// LCD config register
IMG_UINT32 ui32LCDConfig; /* MAR_LCD_CONFIG - 0060 */
// PWM registers
IMG_UINT32 ui32PWMConfig; /* MAR_PWM_CR0 - 0204 */
IMG_UINT32 ui32PWMCR0; /* MAR_PWM_CR0 - 0210 */
IMG_UINT32 ui32PWMDCR0; /* MAR_PWM_DCR0 - 0214 */
IMG_UINT32 ui32PWMPCR0; /* MAR_PWM_PCR0 - 0218 */
IMG_UINT32 ui32PWMCR1; /* MAR_PWM_CR1 - 0220 */
IMG_UINT32 ui32PWMDCR1; /* MAR_PWM_DCR1 - 0224 */
IMG_UINT32 ui32PWMPCR1; /* MAR_PWM_PCR1 - 0228 */
// Bond config register
IMG_UINT32 ui32BondConfig; /* MAR_BOND_CFG - 0304 */
// Interrupt registers
IMG_UINT32 ui32VAINTMask; /* MAR_VAINT_MASKM - 3084 */
IMG_UINT32 ui32GfxINTEnable; /* MAR_GFXINT_ENABLE - 4130 */
} REGISTERS_DATA;
#endif
typedef struct _SYS_SPECIFIC_DATA_
{
IMG_PVOID pvLinRegBaseAddr; /* Linear base for the Marathon registers */
IMG_BOOL bConfigPrefetch; /* Prefetch enabled ? */
IMG_BOOL bConfigTimeout; /* GSB timeout enabled ? */
IMG_BOOL bConfigSRAM; /* SRAM writes to slave ports enabled ? */
IMG_UINT32 ui32BondConfig; /* Bond option */
IMG_BOOL b2DEnabled; /* Clock gating */
IMG_BOOL bAsync2DEnabled;
IMG_BOOL bTAEnabled;
IMG_BOOL b3DEnabled;
#ifdef LOCAL_MEMORY_SELF_REFRESH
IMG_BOOL bM24VAEnabled; // Is video enabled
IMG_BOOL bOverlayEnabled; // Is overlay enabled
IMG_UINT32 uiLocalMemoryUsers; // How many people using LM
IMG_UINT32 uiLocalMemoryTimeout; // How long to delay going into self-refresh
IMG_BOOL bLocalMemoryTimeoutRefresh; // Has someone accessed LM during the delay?
IMG_BOOL bUseLocalMemorySelfRefresh; // Turn on/off on the fly
IMG_UINT32 hLocalMemoryIdleEvent; // Event to signal when local memory not in use
#endif // LOCAL_MEMORY_SELF_REFRESH
IMG_UINT32 ui32CoreClock; /* Maximum Core clock rate */
IMG_UINT32 ui32SysClk; /* Actual system clock value */
IMG_UINT32 ui32PixClk; /* Actual pixel clock value */
IMG_UINT32 ui32MBXDivider; /* Clock dividers for the devices */
IMG_UINT32 ui32M24VADivider;
IMG_UINT32 ui32PixClkDivider;
IMG_UINT32 ui32SRAMChipSelect; /* Set the chip select for SRAM */
IMG_UINT32 ui32VLIOChipSelect; /* Set the chip select for VLIO */
IMG_BOOL bODFBPowerModeActiveLow; /* Enable ODFB Active LOW power mode */
IMG_UINT32 ui32MarathonRevID; /* Marathon Revision ID */
/* SDRAM state */
IMG_UINT32 ui32SDRAMMode;
IMG_BOOL bSDRAMNeedsWaking; /* Set on run->standby with sdram active */
MEM_CONFIGURATION *pMemConfig;
/*
PowerRun Run at default freq
PowerRunSlow Marathon fully active, run at either pixclk or ref freq
PowerSleep All cores inactive, memories shitdown, Marathon still powered
*/
enum {PowerRun, PowerRunSlow, PowerSleep} eMode; /* Marathon state */
LCD_SWITCH_STATE sLCDState;
IMG_UINT32 ui32FBSize; /* Total internal+external */
IMG_UINT32 ui32FBInteralSize; /* Internal size */
IMG_UINT32 ui32PhysBase; /* Physical base address of Marathon */
IMG_UINT32 ui32SPPhysBase; /* Slaveport physical base */
/* Used to map Bulverde/Cotulla registers into process in XScaleMMCSetup*/
volatile IMG_UINT32 *pui32MemCtrl;
IMG_BOOL bCotulla;
IMG_UINT32 ui32MemClk;
/* SDRAM page used for dummy reads to bring SDRAM out of SLEEP mode */
volatile IMG_UINT32 *pui32SDRAMDummyArea;
/* Saved copy of clock gating status, used across Sleep PM changes */
IMG_UINT32 ui32ClkGateMBX;
IMG_UINT32 ui32ClkGateM24VA;
IMG_UINT32 ui32ClkGatePDP_GP;
IMG_UINT32 ui32ClkGatePDP_OP;
/* Saved copy of the address generation regs and sync reg for pre and post pll code */
IMG_UINT32 ui32Str1;
IMG_UINT32 ui32Str2;
IMG_UINT32 ui32Str3;
IMG_UINT32 ui32Sync;
#ifdef SLEEP_MARATHON_OFF
IMG_BOOL bSleepSupport; /* Special sleep mode supported by registry? */
REGISTERS_DATA *pSaveRegister; /* Registers to be saved/restore for sleep state */
#endif
} SYS_SPECIFIC_DATA, * PSYS_SPECIFIC_DATA;
#define GET_MARATHON_SYS_DATA(pData) { SYS_DATA *psSysData; \
SysAcquireData(&psSysData); \
pData = (PSYS_SPECIFIC_DATA) psSysData->pvSysSpecificData; }
/******************************************************* Function prototypes */
#if REDUCE_FREQ_IN_DISP_REFRESH
void SysSDRAMSetStateWithFreqChanges(IMG_UINT32 ui32Mode);
#endif
IMG_VOID SysSDRAMSetState(IMG_UINT32 ui32Mode);
IMG_BOOL XScaleMMCSetup(IMG_UINT32 ui32Freq);
IMG_VOID ChangeSYSCLK(IMG_UINT32 ui32DesiredFreq);
IMG_VOID MarathonBoot();
IMG_BOOL SetPLL(IMG_UINT32 ui32PLL, IMG_UINT32 ui32DesiredFreq, IMG_UINT32 *pui32ResultFreq);
IMG_BOOL DisablePLL(IMG_UINT32 ui32PLL);
IMG_VOID SysPostChangePll();
IMG_VOID SysPreChangePll();
PVRSRV_ERROR SysBoot();
//FIXME
#undef PDUMPSCRIPT
#define PDUMPSCRIPT / ## /
#define PDUMPREGTAG / ## /
#undef PDUMPPOL
#define PDUMPPOL / ## /
#define PDUMPREGMBX / ## /
#define PDUMPTAGS_REG_MSOC 0
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -