📄 sysconfig.h
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/*******************************************************************************
<module>
* Name : system.h
* Title : System Description Header
* Author : J R Morrissey
* Created : 3 March 2003
*
* Copyright : 2003 by Imagination Technologies Limited.
* All rights reserved. No part of this software, either
* material or conceptual may be copied or distributed,
* transmitted, transcribed, stored in a retrieval system
* or translated into any human or computer language in any
* form by any means, electronic, mechanical, manual or
* other-wise, or disclosed to third parties without the
* express written permission of Imagination Technologies
* Limited, Unit 8, HomePark Industrial Estate,
* King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description : This header provides system-specific declarations and macros
*
* Platform : WinCE
*
</module>
********************************************************************************/
#if !defined(__SOCCONFIG_H__)
#define __SOCCONFIG_H__
#define VS_PRODUCT_NAME "Marathon reference"
/* Number of device types available to this system (3D,Display, MPEG) */
#define MAX_DEVICE_IDENTIFIERS 3
/* number of different device memory pools available to this system */
#define MAX_SYSTEM_POOLS 2
#include "syscommon.h"
/*
how much sysmem should the services be able to alloc?
1024 * 4k pages => 4Mb of sysmem
*/
#define SYS_MAX_PAGES 1024
/******************************************************** Marathon device */
/*
value to write to system kicker
*/
#define SYS_KICKER_VALUE MBX1_INT_CMDPROC
/*
Byte offset from device physical base to start
of framebuffer(device) memory region
*/
#define MARATHON_FB_OFFSET 0x00000000
/*
Byte offset from device physical base to start
of device register region (UnCached)
*/
#define MARATHON_REG_OFFSET 0x03FE0000 /* The top end of the address map */
/*
Size in bytes of the device register region
*/
#define MARATHON_REG_SIZE 0x00010000
/*
Byte offset from device physical base to start
of memory mapped slaveports region
*/
#define MARATHON_SP_OFFSET 0x03FF0000
/*
Size in bytes of the slaveports region
*/
#define MARATHON_SP_SIZE 0x00010000
/******************************************************* Marathon MBX device */
#define MBX_REG_OFFSET 0x00004000 /* From Marathon register base */
#define MBX_REG_SIZE 0x00001000 /* MBX register block size */
#define MBX_SP_OFFSET 0x00004000 /* From Slaveport base */
#define MBX_SP_SIZE 0x00003000 /* Total size of Marathon SP's */
/*
MBX Slave Port FIFO Size (in units of `Bits per Write Bus Width')
*/
#define MBX1_SP_FIFO_DWSIZE 510 //dab
/*
Set the amount to reserve - currently taken as a 1/4 of the FIFO
(The value in DWORDs is 1/4 the value in BYTEs, rounded down)
*/
#define MBX1_SP_FIFO_RESERVEBYTES (MBX1_SP_FIFO_DWSIZE & -4)
#define MBX1_SP_FIFO_MAXALLOWEDBYTES (MBX1_SP_FIFO_DWSIZE * 4) - MBX1_SP_FIFO_RESERVEBYTES
/*
Macro to extract FIFO space from HW register value
*/
#define MBX_EXTRACT_FIFO_COUNT(x) ((((x) & MBX1_INT_TA_FREEVCOUNT_MASK) >> MBX1_INT_TA_FREEVCOUNT_SHIFT) | \
(((x) & MBX1_INT_TA_FREE_UPPER_MASK) >> MBX1_INT_TA_FREE_UPPER_SHIFT))
/*
Byte offset from base of MBX slaveports to start of MBX TA slaveport region
*/
#define MBX_TA_SP_DATA_OFFSET 0x00000000
/*
MBX TA slaveport range in bytes
*/
#define MBX_TA_SP_DATA_RANGE 0x00001000
/*
Byte offset from base of MBX slaveports to start of MBX 2D slaveport region
*/
#define MBX_TA_SP_2D_DATA_OFFSET 0x00001000
/*
MBX 2D slaveport range in bytes
*/
#define MBX_TA_SP_2D_DATA_RANGE 0x00001000
/*
byte offset from base of MBX slaveports to start
of MBX TA Control slaveport region
*/
#define MBX_TA_SP_TERM_OFFSET 0x00002000
/*
MBX TA Control slaveport range in bytes
*/
#define MBX_TA_SP_TERM_RANGE 0x00001000
/******************************************************* Marathon PDP device */
/*
Byte offset from device physical base to start of Display registers region
*/
#define DISPLAY_REG_OFFSET 0x00002000
#define DISPLAY_REG_SIZE 0x00001000
/***************************************************** Marathon M24VA device */
#define M24VA_REG_OFFSET 0x00003000 /* From Marathon register base */
#define M24VA_REG_SIZE 0x00001000
#define M24VA_SP_OFFSET 0x00000000 /* From Slaveport base */
#define M24VA_SP_SIZE 0x00002000 /* Total size of Marathon SP's */
/* Slaveport offsets from start of first M24VA SP, range in bytes */
#define M24VA_SP_CMD_OFFSET 0x00000000
#define M24VA_SP_CMD_RANGE 0x00001000
#define M24VA_SP_IDCT_OFFSET 0x00001000
#define M24VA_SP_IDCT_RANGE 0x00001000
/***********************************************************/
#define MBX1_2D_SLAVEPORT_OFFSET_FROM_REGISTERS (MARATHON_SP_OFFSET - MARATHON_REG_OFFSET + \
MBX_TA_SP_2D_DATA_OFFSET)
/*********************************************************** MMU page values */
#define DEV_PAGE_SHIFT (12)
#define DEV_PAGE_SIZE (1<<DEV_PAGE_SHIFT)
#define DEV_PAGE_MASK (DEV_PAGE_SIZE-1)
/**************************** Should be able to remove all these ??????????? */
#define MMU_ARENA_BASE (0)
#define MMU_ARENA_SIZE (32 * 1024 * 1024)
#define MMU_HI_ARENA_BASE (0+MMU_ARENA_SIZE)
#define MMU_HI_ARENA_SIZE (0)
#define MBX_MMU_PTR_SHIFT (3)
#define MBX_MMU_PTRS (1<<MBX_MMU_PTR_SHIFT)
#define MBX_MMU_TT_SHIFT (10)
#define MBX_MMU_TT_ENTRIES (1<<MBX_MMU_TT_SHIFT)
#define MBX1_MMU_PAGE_BITS (12)
#define MBX1_MMU_TAG_BITS (5)
#define MBX1_MMU_INDEX_BITS (MBX_MMU_TT_SHIFT + MBX_MMU_PTR_SHIFT - MBX1_MMU_TAG_BITS)
#define MBX1_MMU_INDEX_MASK ((1<<MBX1_MMU_INDEX_BITS)-1)
#define MBX1_MMU_TAG_MASK ((1<<MBX1_MMU_TAG_BITS)-1)
/*****************************************************************************
* system specific data structure
*****************************************************************************/
/*****************************************************************************/
/************************ Defines Required for Marathon **********************/
/*****************************************************************************/
/* New ones */
IMG_UINT32 SysSetPixClkFrequency(IMG_UINT32 ui32Freq); //was DevSetPixClkFrequency
IMG_VOID SysMemoryDrain(); //was DevMemoryDrain
#ifdef SUPPORT_POWER_STATE
IMG_VOID SysSetPowerState(PVR_POWER_STATE eState); //was DevSetPowerState
#endif
IMG_UINT32 SysDisableInterrupts();
IMG_UINT32 SysEnableInterrupts();
#define SYS_SDRAM_POWER_SLEEP 0
#define SYS_SDRAM_POWER_SHUTDOWN 1
#define SYS_SDRAM_POWER_ACTIVE 2
typedef enum _SYS_CLOCK_EDGE_
{
SYS_RISING,
SYS_FALLING
} SYS_CLOCK_EDGE;
typedef enum _SYS_DRIVE_STRENGTH_
{
SYS_3MA,
SYS_6MA_10MA
} SYS_DRIVE_STRENGTH;
typedef enum _SYS_HOST_LCD_FORMAT_
{
SYS_HOST_LCD_555,
SYS_HOST_LCD_556,
SYS_HOST_LCD_565,
SYS_HOST_LCD_655,
SYS_HOST_LCD_665,
SYS_HOST_LCD_666
} SYS_GIB_FORMAT;
typedef enum _SYS_LCD_SOURCE_
{
SYS_SOURCE_PDP,
SYS_SOURCE_HOST
} SYS_LCD_SOURCE;
typedef struct _SYS_LCD_CONFIG_
{
SYS_CLOCK_EDGE eDENPolarity;
SYS_CLOCK_EDGE eFCLKPolarity;
SYS_CLOCK_EDGE eLCLKPolarity;
SYS_CLOCK_EDGE eDataPolarity;
IMG_BOOL bActive;
SYS_DRIVE_STRENGTH eDataStrength;
SYS_DRIVE_STRENGTH eClockStrength;
SYS_LCD_SOURCE eSource;
} SYS_LCD_CONFIG, *PSYS_LCD_CONFIG;
IMG_VOID SysWriteLEDData(IMG_UINT32 ui32Data); //was DevWriteLEDData
IMG_VOID SysWriteLEDBits(IMG_UINT8 ui8Data); //was DevWriteLEDBits
IMG_UINT8 SysReadUserSwitches(IMG_VOID); //was DevReadUserSwitches
IMG_UINT32 SysSetPWM(IMG_UINT32 ui32PWM, IMG_UINT32 ui32Period, IMG_UINT32 ui32DutyCycle); //was DevSetPWM
IMG_VOID SysConfigLCD(IMG_UINT32 ui32LCD, PSYS_LCD_CONFIG psConfig); //was DevConfigLCD
IMG_VOID SysConfigHostLCDFormat(SYS_GIB_FORMAT eFormat); //was DevConfigHostLCDFormat
IMG_VOID SysDisableVBlank();
IMG_VOID SysEnableVBlank();
/********************************************** External function prototypes */
extern IMG_VOID MBXIsr (PVRSRV_DEV_INFO *psDevInfo);
/************************************************ Other system layer defines */
#include "marmemory.h"
#include "marathon.h"
#endif /* __SOCCONFIG_H__ */
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