📄 marmemory.h
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/*******************************************************************************
* Name : marmemory.h
* Title : Marathon memory defines
* Author : Tim Rowley
* Created : 21st May 2003
*
* Copyright : 2003 by Imagination Technologies Limited.
* All rights reserved. No part of this software, either
* material or conceptual may be copied or distributed,
* transmitted, transcribed, stored in a retrieval system
* or translated into any human or computer language in any
* form by any means, electronic, mechanical, manual or
* other-wise, or disclosed to third parties without the
* express written permission of Imagination Technologies
* Limited, Unit 8, HomePark Industrial Estate,
* King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description : Marathon memory defines
*
* Platform : Generic
*
* NOTE: THIS FILE ALSO EXISTS IN Consumer\Tests\WinCE\memory\tux\memtest
*
* Modifications:-
* $Log: marmemory.h $
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*
* --- Revision Logs Removed ---
*******************************************************************************/
/*************************************************** Memory timings structure */
#ifndef DEFINE_MEMORY_TABLES
typedef struct
{
IMG_UINT32 ui32UDimmSize;
IMG_UINT32 ui32CAS2Threshold;
IMG_UINT32 ui32CAS3Threshold;
IMG_UINT32 ui32BankBits;
IMG_UINT32 ui32RowBits;
IMG_UINT32 ui32ColBits;
IMG_UINT32 ui32TRAS;
IMG_UINT32 ui32TRP;
IMG_UINT32 ui32TRCD;
IMG_UINT32 ui32TRC;
IMG_UINT32 ui32TDPLClks;
IMG_UINT32 ui32Refresh;
IMG_UINT32 ui32CKEWait;
IMG_UINT32 ui32MaxFreq;
} MEM_CONFIGURATION;
#endif
/***************************************************** Memory timings tables */
#ifdef DEFINE_MEMORY_TABLES
/* Timings for FPGA SDRAM Micron MT48LC8M16A2-75 */
MEM_CONFIGURATION sMemConfigFPGAMicronMT48LC8M16A2 =
{
(16*1024*1024), //MAR_UDIMM_SIZE
0, //MAR_CAS2_THRESHOLD
100000000, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
9, //MAR_COL_BITS
44, //MAR_TRAS
20, //MAR_TRP
20, //MAR_TRCD
66, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
133333333 //MAR_MAX_FREQ (limited by Marathon)
};
/* Timings for uDIMM #1 Samsung K4S641632F-TL75 */
MEM_CONFIGURATION sMemConfigSamsungK4S641632F =
{
(16*1024*1024), //MAR_UDIMM_SIZE
0, //MAR_CAS2_THRESHOLD
100000000, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
8, //MAR_COL_BITS
45, //MAR_TRAS
20, //MAR_TRP
20, //MAR_TRCD
65, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
133333333 //MAR_MAX_FREQ (limited by Marathon - 142857142MHz is SDRAM limit)
};
/* Timings for uDIMM #2 Samsung K4S56163LC-RG1L */
MEM_CONFIGURATION sMemConfigSamsungK4S56163LC =
{
(64*1024*1024), //MAR_UDIMM_SIZE
40000000, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
9, //MAR_COL_BITS
60, //MAR_TRAS
24, //MAR_TRP
24, //MAR_TRCD
84, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ
};
#if 0
/* Timings for uDIMM #3 Samsung K4S64323LF-SN1L */
MEM_CONFIGURATION sMemConfigSamsungK4S64323LF =
{
(8*1024*1024), //MAR_UDIMM_SIZE
40000000, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
13, //MAR_ROW_BITS
9, //MAR_COL_BITS
60, //MAR_TRAS
24, //MAR_TRP
24, //MAR_TRCD
84, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
105263157 //MAR_MAX_FREQ
};
#else
/* Timings for uDIMM #3a Infineon HYB/E 25L128160AC */
MEM_CONFIGURATION sMemConfigInfineon25L128160AC =
{
(32*1024*1024), //MAR_UDIMM_SIZE
50000000, //MAR_CAS2_THRESHOLD
105263157, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
9, //MAR_COL_BITS
45, //MAR_TRAS
19, //MAR_TRP
19, //MAR_TRCD
67, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
133333333 //MAR_MAX_FREQ
};
#endif
/* Timings for uDIMM #4 Samsung K4M28163PD-RG1L */
MEM_CONFIGURATION sMemConfigSamsungK4M28163PD =
{
(32*1024*1024), //MAR_UDIMM_SIZE
40000000, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
11, //MAR_ROW_BITS
8, //MAR_COL_BITS
60, //MAR_TRAS
29, //MAR_TRP
29, //MAR_TRCD
90, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ
};
/* Timings for uDIMM #5 Samsung K4M56323LD-MG1L */
MEM_CONFIGURATION sMemConfigSamsungK4M56323LD =
{
(32*1024*1024), //MAR_UDIMM_SIZE
40000000, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
9, //MAR_COL_BITS
60, //MAR_TRAS
24, //MAR_TRP
24, //MAR_TRCD
84, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ (limited by Marathon since 1.8V IO - 105263157MHz is SDRAM limit)
};
/* Timings for uDIMM #6 Elpida EDL2516CBBH-10E */
MEM_CONFIGURATION sMemConfigElpidaEDL2516CBBH =
{
(64*1024*1024), //MAR_UDIMM_SIZE
0, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
9, //MAR_COL_BITS
60, //MAR_TRAS
30, //MAR_TRP
30, //MAR_TRCD
90, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ
};
/* Timings for uDIMM #7 Samsung K4S51323LC-MS1L */
MEM_CONFIGURATION sMemConfigSamsungK4S51323LC =
{
(64*1024*1024), //MAR_UDIMM_SIZE
40000000, //MAR_CAS2_THRESHOLD
83333333, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
13, //MAR_ROW_BITS
9, //MAR_COL_BITS
60, //MAR_TRAS
24, //MAR_TRP
24, //MAR_TRCD
84, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ
};
/* Timings for uDIMM #8 Samsung K4S51153LC */
MEM_CONFIGURATION sMemConfigSamsungK4S51153LC =
{
(16*1024*1024), //MAR_UDIMM_SIZE //Carbonado Mem
40000000, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
8, //MAR_COL_BITS //Carbonado Mem
60, //MAR_TRAS
24, //MAR_TRP
24, //MAR_TRCD
84, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ (limited by Marathon since 1.8V IO - 105263157MHz is SDRAM limit)
};
/* Timings for uDIMM #9 Emerald stacked local memory */
MEM_CONFIGURATION sMemConfigEmerald =
{
(16*1024*1024), //MAR_UDIMM_SIZE
0, //MAR_CAS2_THRESHOLD
66666666, //MAR_CAS3_THRESHOLD
2, //MAR_BANK_BITS
12, //MAR_ROW_BITS
8, //MAR_COL_BITS
60, //MAR_TRAS
30, //MAR_TRP
30, //MAR_TRCD
90, //MAR_TRC
2, //MAR_TDPL_CLKS
64000000, //MAR_REFRESH
2, //MAR_CKE_WAIT
100000000 //MAR_MAX_FREQ
};
/* Memory configuration table */
MEM_CONFIGURATION *gAllMemConfigs[] =
{
&sMemConfigFPGAMicronMT48LC8M16A2, //FPGA SDRAM Micron MT48LC8M16A2-75
&sMemConfigSamsungK4S641632F, //uDIMM #1 Samsung K4S641632F-TL75
&sMemConfigSamsungK4S56163LC, //uDIMM #2 Samsung K4S56163LC-RG1L
#if 0
&sMemConfigSamsungK4S64323LF, //uDIMM #3 Samsung K4S64323LF-SN1L
#else
&sMemConfigInfineon25L128160AC, //uDIMM #3a Infineon 25L128160AC
#endif
&sMemConfigSamsungK4M28163PD, //uDIMM #4 Samsung K4M28163PD-RG1L
&sMemConfigSamsungK4M56323LD, //uDIMM #5 Samsung K4M56323LD-MG1L
&sMemConfigElpidaEDL2516CBBH, //uDIMM #6 Elpida EDL2516CBBH-10E
&sMemConfigSamsungK4S51323LC, //uDIMM #7 Samsung K4S51323LC-MS1L
&sMemConfigSamsungK4S51153LC, //uDIMM #8 Samsung K4S51153LC
&sMemConfigEmerald, //uDIMM #9 Emerald stacked local memory.
};
#endif /* #ifdef DEFINE_MEMORY_TABLES */
/*****************************************************************************/
/*****************************************************************************/
/*****************************************************************************/
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