📄 registers.c
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psTARegs[D3DM_SWTAREG_YCLIP].ui32RegVal = (dwHeight << MBX1_TA_YCLIPMAXSHIFT) &
(~MBX1_TA_YCLIPMAXCLR);
/*
Setup micro-tile max X/Y extent in the TA config register
*/
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal &= MBX1_TACONFIG_RENDERWIDTHCLRMASK &
MBX1_TACONFIG_RENDERHEIGHTCLRMASK;
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= ((ps3DIFSharedData->ui32TilesX - 1)
<< MBX1_TACONFIG_RENDERWIDTHSHIFT)
& (~MBX1_TACONFIG_RENDERWIDTHCLRMASK);
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= ((ps3DIFSharedData->ui32TilesY - 1)
<< MBX1_TACONFIG_RENDERHEIGHTSHIFT)
& (~MBX1_TACONFIG_RENDERHEIGHTCLRMASK);
/*
Set Z-LoadStore X extent
*/
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal |= (((ps3DIFSharedData->ui32XTilesPerMT *
ps3DIFSharedData->ui32MTilesX)-1)
<< MBX1_ZLOADSTORE_XEXTENTSHIFT);
#if defined(SUPPORT_MBX1)
/*
Setup render size
*/
ps3DRegs[D3DM_SW3DREG_3DSCREENSIZE].ui32RegVal &= ~(MBX1_3DSCREENSIZE_RENDER_WIDTH_MASK |
MBX1_3DSCREENSIZE_RENDER_HEIGHT_MASK);
ps3DRegs[D3DM_SW3DREG_3DSCREENSIZE].ui32RegVal |= ((ps3DIFSharedData->ui32TilesX - 1) << MBX1_3DSCREENSIZE_RENDER_WIDTH_SHIFT) &
MBX1_3DSCREENSIZE_RENDER_WIDTH_MASK;
ps3DRegs[D3DM_SW3DREG_3DSCREENSIZE].ui32RegVal |= ((ps3DIFSharedData->ui32TilesY - 1) << MBX1_3DSCREENSIZE_RENDER_HEIGHT_SHIFT) &
MBX1_3DSCREENSIZE_RENDER_HEIGHT_MASK;
#endif
/*
Reset the current framebuffer pack-mode (format) and alpha-handling
controls
*/
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal &= MBX1_FBCTL_PACKMODECLR;
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal &= MBX1_FBCTL_KVALCLR &
MBX1_FBCTL_ALPHATHRESHCLR;
/*
Setup framebuffer configuraton based upon the render-target pixelformat
*/
switch (psRenderTarget->eFormat)
{
case D3DMFMT_R8G8B8:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE888;
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal |= MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
case D3DMFMT_A8R8G8B8:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE8888;
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal &= ~MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
case D3DMFMT_X8R8G8B8:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODEK888;
/*
If our render surface is also a 0888 texture, force it
to be opaque in 8888 (write a constant alpha value of 0xFF)
*/
if (psRenderTarget->dwUsage & D3DMUSAGE_TEXTURE)
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= 0xFF << MBX1_FBCTL_KVALSHIFT;
}
break;
}
case D3DMFMT_A1R5G5B5:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE1555;
/*
Alpha-Threshold of 128, any internal value with greater
than 50% transparency will be written out as opaque.
*/
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= 0x80 << MBX1_FBCTL_ALPHATHRESHSHIFT;
/*
Remove the force alpha flag.
*/
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal &= ~MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
case D3DMFMT_X1R5G5B5:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE555;
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal |= MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
case D3DMFMT_R5G6B5:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE565;
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal |= MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
case D3DMFMT_A4R4G4B4:
{
ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_PACKMODE4444;
ps3DRegs[D3DM_SW3DREG_BLENDCTL].ui32RegVal &= ~MBX1_3DBLENDCONTROL_FORCEALPHA;
break;
}
default:
{
//FIXME: error
break;
}
}
/*
Set render line-stride (in 4byte units)
*/
ps3DRegs[D3DM_SW3DREG_FBLINESTRIDE].ui32RegVal = psRenderTarget->dwStrideByte >> MBX1_FBLINESTRIDE_ALIGNSHIFT;
/*
Set render target address (a 4-byte aligned offset from the framebuffer
base address)
*/
ps3DRegs[D3DM_SW3DREG_FBSTART].ui32RegVal = (psRenderTarget->psMemInfo->uiDevAddr.uiAddr)
& MBX1_FBSTART_MASK;
D3DM_DPF((DPF_MESSAGE, "***** Setting FB Render target to 0x%8.8X",psRenderTarget->psMemInfo->uiDevAddr.uiAddr));
}
/*****************************************************************************
FUNCTION : SetupSceneRegs
PURPOSE : Sets up required registers before a render is queued
PARAMETERS : psContext - The current 3D rendering context
RETURNS : None.
*****************************************************************************/
void SetupSceneRegs(LPD3DM_CONTEXT psContext)
{
PVR3DIF_PARAMBUFFER *psParamBuffer;
PVR3DIF_SHAREDDATA *psSharedData;
PVRSRV_DEV_INFO *psDevInfo;
PVRSRV_HWREG *ps3DRegs;
PVRSRV_HWREG *psTARegs;
PVRSRV_TARENDERINFO *psTARenderInfo;
LPD3DM_SURFACE psRenderTarget;
DWORD dwCurrentRenderData;
psRenderTarget = psContext->psCurrentRenderTarget;
psDevInfo = GetDevInfo(psContext);
ps3DRegs = psContext->ps3DRegs;
psTARegs = psContext->psTARegs;
psParamBuffer = (PVR3DIF_PARAMBUFFER *)psDevInfo->sDeviceSpecific.s3D.hParamBuffer;
psTARenderInfo = psRenderTarget->sDescription.sSurface.psTARenderInfo;
psSharedData = psTARenderInfo->psSharedData;
dwCurrentRenderData = psSharedData->ui32CurrentRenderData;
/*
Deal with Z setup
*/
if(psContext->psCurrentDepthBuffer && psContext->psCurrentDepthBuffer->psMemInfo)
{
/*
If we have a Zbuffer, then do a ZStore
*/
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= MBX1_TACONFIG_ZSTORE;
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal |= MBX1_ZLOADSTORE_ZSTORE;
ps3DRegs[D3DM_SW3DREG_ZBASEADDR].ui32RegVal = psContext->psCurrentDepthBuffer->psMemInfo->uiDevAddr.uiAddr;
/*
Clear "No external Z-Buffer" flag in ZLS control reg
*/
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal &= ~MBX1_ZLOADSTORE_ZFORMAT_NO_EXT_Z;
}
else
{
/*
Clear ZStore flags
*/
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal &= ~MBX1_TACONFIG_ZSTORE;
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal &= ~MBX1_ZLOADSTORE_ZSTORE;
/*
Mark ZLSControl reg with "No external Z-Buffer" flag
*/
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal |= MBX1_ZLOADSTORE_ZFORMAT_NO_EXT_Z;
}
if(psRenderTarget->sDescription.sSurface.dwClearFlags & D3DM_SURFACE_CLEARFLAGS_FULLSCREEN_DEPTH)
{
/*
There's been a Z-clear, so don't Z-Load
*/
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal &= ~MBX1_TACONFIG_ZLOAD;
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal &= ~MBX1_ZLOADSTORE_ZLOAD;
}
else
{
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= MBX1_TACONFIG_ZLOAD;
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal |= MBX1_ZLOADSTORE_ZLOAD;
}
/* Enable or disable dithering for this scene */
if(psContext->sTState.dwRSFlags & TSTATE_RSFLAGS_DITHER)
{
/* Dither is enabled so enable hardware dithering */
psContext->ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal |= MBX1_FBCTL_DITHER;
}
else
{
/* Dither is disabled */
psContext->ps3DRegs[D3DM_SW3DREG_FBCTL].ui32RegVal &= ~MBX1_FBCTL_DITHER;
}
/*
Set depth clear reg value
*/
ps3DRegs[D3DM_SW3DREG_3D_ZL_BACKGROUND_DEPTH].ui32RegVal = FLOAT_TO_LONG(psContext->sTState.fLastClearZ) | 0x00000001;
/*
Set 3D-core Region-header base addresses
*/
ps3DRegs[D3DM_SW3DREG_RGNBASE].ui32RegVal = psSharedData->asRgnHeaderDevVAddr[dwCurrentRenderData].uiAddr & MBX1_RGNBASE_MASK;
/*
Set 3D-core object data base addresses
*/
ps3DRegs[D3DM_SW3DREG_OBJBASE].ui32RegVal = psParamBuffer->ParamDevVAddr.uiAddr;
/* Reset the render info modify reg status */
psSharedData->ui32MidSceneModRegCount = 0;
}
/*****************************************************************************
FUNCTION : SetupHWRegs
PURPOSE : Perform one-time initialisation of the context register arrays
PARAMETERS : psContext - The current 3D rendering context
RETURNS : None.
*****************************************************************************/
IMG_VOID SetupHWRegs(LPD3DM_CONTEXT psContext)
{
PVRSRV_DEV_INFO *psDevInfo;
PVRSRV_HWREG *ps3DRegs;
PVRSRV_HWREG *psTARegs;
float fTemp;
IMG_UINT32 ui32ForceZ;
IMG_CHAR szTemp[256];
psDevInfo = GetDevInfo(psContext);
ps3DRegs = psContext->ps3DRegs;
psTARegs = psContext->psTARegs;
/*
Setup default 3D-core register settings.
*/
SetupSWRegDefaults(ps3DRegs,
(sizeof(psDefault3DRegs)/sizeof(*psDefault3DRegs)),
psDefault3DRegs);
/*
Setup default TA register settings.
*/
SetupSWRegDefaults(psTARegs,
(sizeof(psDefaultTARegs)/sizeof(*psDefaultTARegs)),
psDefaultTARegs);
/*
FPU & TSP sample at pixel centre?
*/
if (psContext->sRegData.dwFlags & D3DMREG_ENABLE_ISPHALFOFFSET)
{
ps3DRegs[D3DM_SW3DREG_3DPIXSAMP].ui32RegVal |= MBX1_PIXSAMP_FPUPIXEL |
MBX1_PIXSAMP_TSPPIXEL |
MBX1_PIXSAMP_TSPTEXEL;
}
/*
Setup culling FPU & perspective FPU values
*/
fTemp = 1.0e-20f;
ps3DRegs[D3DM_SW3DREG_FPUCULLVAL].ui32RegVal = *((PDWORD) &fTemp);
ps3DRegs[D3DM_SW3DREG_FPUPERPVAL].ui32RegVal = *((PDWORD) &fTemp);
if(psContext->sRegData.dwIFlags & D3DMREGI_DISABLE_TSP)
{
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal = MBX1_ZLOADSTORE_ZONLYRENDER;
}
/* Check if we are forcing Zbuffer creation */
sprintf(szTemp, "%s%s", POWERVR_REG_ROOT, D3DM_REGAPPHINTCOMMON_ROOT);
D3DMGetAppHint(0, szTemp, "ForceExternalZBuffer", &ui32ForceZ);
if(!ui32ForceZ)
{
ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal = MBX1_ZLOADSTORE_ZLOAD | MBX1_ZLOADSTORE_ZFORMAT_NO_EXT_Z;
}
/*
Enable TA small object culling?
NB: To save parameter-space, the TA can cull very-small objects that do
not cross the pixel-sampling center.
*/
if(psContext->sRegData.dwFlags & D3DMREG_ENABLE_TASMALLCULL)
{
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= MBX1_TACONFIG_SMALLOBJCULL;
}
/*
Enable TA coordinate snapping?
NB: The TA can snap X/Y coordinates to 1/16th pixels.
*/
if(psContext->sRegData.dwFlags & D3DMREG_DISABLE_TASNAPPING)
{
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= MBX1_TACONFIG_DISABLESNAPPING;
}
/*
Sample at pixel centre?
NB: The TA can use a pixel-sample center of (0,0) or (.5, .5)
*/
if (psContext->sRegData.dwFlags & D3DMREG_ENABLE_TAHALFOFFSET)
{
psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal |= MBX1_TACONFIG_PIXELCENTRE;
}
}
/*****************************************************************************
FUNCTION : SetupMidSceneModifyRegs
PURPOSE : Perform set up of mod registers for mid scene render
PARAMETERS : psContext - The current 3D rendering context
RETURNS : None.
*****************************************************************************/
void SetupMidSceneModifyRegs(LPD3DM_CONTEXT psContext)
{
PVRSRV_HWREG *ps3DRegs = psContext->ps3DRegs;
LPD3DM_SURFACE psRenderTarget = psContext->psCurrentRenderTarget;
PPVRSRV_3DSHAREDDATA psSharedData = psRenderTarget->sDescription.sSurface.psTARenderInfo->psSharedData;
PVRSRV_HWREG *psModRegs = psSharedData->asMidSceneModRegs;
/* Do a ZStore */
psModRegs[0].ui32RegAddr = MBX1_GLOBREG_ZLOADSTORE;
psModRegs[0].ui32RegVal = (ps3DRegs[D3DM_SW3DREG_ZLOADSTORE].ui32RegVal | MBX1_ZLOADSTORE_ZSTORE) &
(~MBX1_ZLOADSTORE_ZFORMAT_NO_EXT_Z);
/* Set Z base address */
psModRegs[1].ui32RegAddr = MBX1_GLOBREG_ZBASEADDR;
psModRegs[1].ui32RegVal = psContext->psCurrentDepthBuffer->psMemInfo->uiDevAddr.uiAddr;
/* Flag required mods in render info */
psSharedData->ui32MidSceneModRegCount = D3DM_SWMODREG_COUNT;
}
/*****************************************************************************
End of file (Registers.c)
*****************************************************************************/
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