registers.c

Lido PXA270平台开发板的最新BSP,包括源代码

/******************************************************************************
<module>
* Name         : Registers.c
* Title        : Register-setup and management
* Author(s)    : Imagination Technologies
* Created      : 2 March 2004
*
* Copyright    : 2004 by Imagination Technologies Limited.
*                All rights reserved.  No part of this software, either
*                material or conceptual may be copied or distributed,
*                transmitted, transcribed, stored in a retrieval system
*                or translated into any human or computer language in any
*                form by any means, electronic, mechanical, manual or
*                other-wise, or disclosed to third parties without the
*                express written permission of Imagination Technologies
*                Limited, Unit 8, HomePark Industrial Estate,
*                King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description  :  Register-setup and management
*
* Platform     : Windows CE
*
</module>

 $Log: registers.c $

********************************************************************************/
#include "context.h"

/****************************************************************************
 Some default defs.
*****************************************************************************/
#define MBX1_3DPIXSAMP_DEFAULT	(MBX1_PIXSAMP_TSPTEXEL | \
								 MBX1_PIXSAMP_DCALCTILEXY)

#define MBX1_BLENDCTL_DEFAULT	(MBX1_3DBLENDCONTROL_FORCEALPHA)

/*
	TA configuration defaults:

	Invert offset-colour alpha-channel (MBX fog-blend sense if inverse of D3D)
	Disable 1/16th pixel coordinate snapping.
*/
#define MBX1_TACONFIG_DEFAULT	(MBX1_TACONFIG_INVERTOFFSETALPHA | \
								 MBX1_TACONFIG_COMPLETEONTERM	 | \
								 MBX1_TACONFIG_ZLOAD)

/*
	Default TA comparison/clamp value, for guarding against RHW = 0.0
	in perspective correct texturing mode.
*/

#define MBX1_TARHWCLAMP_DEFAULT	((0x0DA24260L /* 1e-30f */ << MBX1_TA_RHWCLAMP_SHIFT) & \
								 MBX1_TA_RHWCLAMP_MASK)

#define MBX1_TARHWCOMP_DEFAULT	((0x0DA24260L /* 1e-30f */ << MBX1_TA_RHWCOMP_SHIFT) & \
								 MBX1_TA_RHWCOMP_MASK)

/*
	Default TA global object-list control
*/
#define MBX1_TAGLOBAL_LIST_CTRL_DEFAULT		(0x00640040L)

/*
	Default TA/3D-core register values

	NB:	Each entry consists of the index within the context SW register array,
		and the corresponding HW register address and default value.
*/
SWREG_DEFAULT psDefault3DRegs[] =
{
	{	/* Pointer to the list of region headers for the tiles to be rendered */
		D3DM_SW3DREG_RGNBASE,
		MBX1_GLOBREG_RGNBASE,
		0
	},

	{	/* depth load/store control */
		D3DM_SW3DREG_ZLOADSTORE,
		MBX1_GLOBREG_ZLOADSTORE,
		0
	},

	{	/* ??? */
		D3DM_SW3DREG_FPUPERPVAL,
		MBX1_GLOBREG_FPUPERPVAL,
		0
	},

	{	/* ??? */
		D3DM_SW3DREG_FPUCULLVAL,
		MBX1_GLOBREG_FPUCULLVAL,
		0
	},

	{	/* pixel/texel sampling rules (i.e. sample at 0.0, 0.0 or 0.5, 0.5) */
		D3DM_SW3DREG_3DPIXSAMP,				
		MBX1_GLOBREG_3DPIXSAMP,				
		MBX1_3DPIXSAMP_DEFAULT 
	},

	{	/* R8G8B8 Vertex-fog colour */
		D3DM_SW3DREG_FOGCOLVERT,
		MBX1_GLOBREG_FOGCOLVERT,				
		0 
	},

	{	/* fullscreen super-sampling down-scale controls */
		D3DM_SW3DREG_SCALERCTL,				
		MBX1_GLOBREG_SCALERCTL,				
		0 
	},

	{
		D3DM_SW3DREG_BLENDCTL,				
		MBX1_GLOBREG_BLENDCTL,				
		MBX1_BLENDCTL_DEFAULT 
	},

	{
		D3DM_SW3DREG_ARGBSUM,					
		MBX1_GLOBREG_ARGBSUM,					
		0 
	},

	{
		D3DM_SW3DREG_FBCTL,					
		MBX1_GLOBREG_FBCTL,					
		0 
	},

	{
		D3DM_SW3DREG_FBXCLIP,					
		MBX1_GLOBREG_FBXCLIP,					
		0 
	},

	{
		D3DM_SW3DREG_FBYCLIP,					
		MBX1_GLOBREG_FBYCLIP,					
		0 
	},

	{
		D3DM_SW3DREG_FBSTART,					
		MBX1_GLOBREG_FBSTART,					
		0 
	},

	{
		D3DM_SW3DREG_FBLINESTRIDE,			
		MBX1_GLOBREG_FBLINESTRIDE,			
		0 
	},

	{
		D3DM_SW3DREG_ZBASEADDR,				
		MBX1_GLOBREG_ZBASEADDR,				
		0 
	},

	{
		D3DM_SW3DREG_3DFLATSHADEDCS,			
		MBX1_GLOBREG_3DFLATSHADEDCS,			
		MBX1_3DFLATSHADEDCS_D3D 
	},

	{
		D3DM_SW3DREG_3D_ZL_BACKGROUND_DEPTH,	
		MBX1_GLOBREG_3D_ZL_BACKGROUND_DEPTH,	
		0 
	},
	{
		D3DM_SW3DREG_3D_ZL_BACKGROUND_TAG,	
		MBX1_GLOBREG_3D_ZL_BACKGROUND_TAG,	
		MBX1_3DZLBG_TAG_OBJ_TEXTURED			| 
		(8 << MBX1_3DZLBG_TAG_OBJ_MASK_SHIFT)	|
		0
	},
	{
		D3DM_SW3DREG_OBJBASE,	
		MBX1_GLOBREG_OBJBASE,	
		0
	},	

	{	/* Render width and height (in pixels) */
		D3DM_SW3DREG_3DSCREENSIZE,
		MBX1_GLOBREG_3DSCREENSIZE,
		0 
	},

	{	/* Last sw reg will kick off the render */ 
		D3DM_SW3DREG_STARTRENDER,		
		MBX1_GLOBREG_STARTRENDER,		
		1 
	}
};												 

SWREG_DEFAULT psDefaultTARegs[] =
{
	{	/* Base of tail-pointer space - setup in SetupRenderTargetRegs */
		D3DM_SWTAREG_TAILPTRBASE,				
		MBX1_TAGLOBREG_TAILPTRBASE,				
		0 
	},

	{	/* Base of region-header space - setup in SetupRenderTargetRegs */
		D3DM_SWTAREG_REGION_BASE,				
		MBX1_TAGLOBREG_REGION_BASE,				
		0 
	},

	{	/* TA global object-control */
		D3DM_SWTAREG_GLOBAL_LIST_CTRL,		
		MBX1_TAGLOBREG_GLOBAL_LIST_CTRL,		
		MBX1_TAGLOBAL_LIST_CTRL_DEFAULT 
	},

	{	/* TA screen X-min/max pixel clip  - setup in SetupRenderTargetRegs */
		D3DM_SWTAREG_XCLIP,					
		MBX1_TAGLOBREG_XCLIP,					
		0 
	},

	{	/* TA screen Y-min/max pixel clip  - setup in SetupRenderTargetRegs */
		D3DM_SWTAREG_YCLIP,					
		MBX1_TAGLOBREG_YCLIP,					
		0 
	},

	{	/* TA RHW clamp value (a float) */
		D3DM_SWTAREG_RHWCLAMP,				
		MBX1_TAGLOBREG_RHWCLAMP,				
		MBX1_TARHWCLAMP_DEFAULT 
	},

	{	/* TA RHW compare value (a float) */
		D3DM_SWTAREG_RHWCOMP,					
		MBX1_TAGLOBREG_RHWCOMP,					
		MBX1_TARHWCOMP_DEFAULT 
	},

	{	/* General TA control/configuration */
		D3DM_SWTAREG_CONFIG,					
		MBX1_TAGLOBREG_CONFIG,					
		MBX1_TACONFIG_DEFAULT
	}
};

/*****************************************************************************
 FUNCTION	: SetupSWRegDefaults
    
 PURPOSE	: Initialises a context SW register array 

 PARAMETERS	: psSWRegs		- The array of register values to be setup
			  dwNumRegs		- How many registers to initialise
			  psDefaults	- The indices and default values to use
 			  
 RETURNS	: void
*****************************************************************************/
void SetupSWRegDefaults(PVRSRV_HWREG	*psSWRegs,
						DWORD			dwNumRegs,
						PSWREG_DEFAULT	psDefaults)
{
	PSWREG_DEFAULT	psRegDefault;
	DWORD			i;

	for	(i = 0; i < dwNumRegs; i++)
	{
		psRegDefault = &psDefaults[i];
		psSWRegs[psRegDefault->dwSWRegIdx] = psRegDefault->sReg;
	}
}

/*****************************************************************************
 FUNCTION	: SetupRenderTargetRegs
    
 PURPOSE	: Sets up h/w registers related to the chosen render-target, e.g
				
			  o  Render dimensions
			  o  Render stride
			  o  Render pixel packmode (i.e. pixel-format)
			  o  Render address

 PARAMETERS	: psContext		- The current 3D rendering context
 			  
 RETURNS	: void
*****************************************************************************/
void SetupRenderTargetRegs(LPD3DM_CONTEXT psContext)
{
	PVRSRV_DEV_LOCATION	*psDevLoc;
	PVRSRV_DEV_INFO		*psDevInfo;
	LPD3DM_SURFACE		psRenderTarget;
	PVRSRV_HWREG		*ps3DRegs;
	PVRSRV_HWREG		*psTARegs;
	DWORD				dwWidth;
	DWORD				dwHeight;
	DWORD				dwCurrentRenderData;
	PVR3DIF_SHAREDDATA  *ps3DIFSharedData;

	psDevInfo			= GetDevInfo(psContext);
	psDevLoc			= &psDevInfo->sDevLocation;
	ps3DRegs			= psContext->ps3DRegs;
	psTARegs			= psContext->psTARegs;
	psRenderTarget		= psContext->psCurrentRenderTarget;
	ps3DIFSharedData	= psRenderTarget->sDescription.sSurface.psTARenderInfo->psSharedData;
	dwCurrentRenderData = ps3DIFSharedData->ui32CurrentRenderData;

	/*
		Set TA tail-pointer base addresses
	*/
	psTARegs[D3DM_SWTAREG_TAILPTRBASE].ui32RegVal = 
		ps3DIFSharedData->TailPtrDevVAddr.uiAddr & MBX1_TA_TAILPTRBASE_MASK;

	/*
		Determine the effective render dimensions (in pixels)
	*/
	dwWidth		 = psRenderTarget->dwWidth;
	dwHeight	 = psRenderTarget->dwHeight;

	/*
		Enable TA up-scaling and 3D-core down-scaling as appropriate
	*/
	ps3DRegs[D3DM_SW3DREG_3DPIXSAMP].ui32RegVal &= ~(MBX1_PIXSAMP_FASTAA);
    ps3DRegs[D3DM_SW3DREG_SCALERCTL].ui32RegVal &= ~(MBX1_SCALERCTL_HSCALE | 
                                                   MBX1_SCALERCTL_VSCALE);
	psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal    &= ~(MBX1_TACONFIG_SUPERSAMPLEX | 
                                                   MBX1_TACONFIG_SUPERSAMPLEY);

	/*
		fast AA in X?
	*/
	if (psContext->dwFlags & D3DM_CONTEXT_SWFLAGS_ENABLE_FASTAA)
	{
		ps3DRegs[D3DM_SW3DREG_3DPIXSAMP].ui32RegVal |= MBX1_PIXSAMP_FASTAA;
	}

	/*
		super sample in X?
	*/
	if	(psContext->dwFlags & D3DM_CONTEXT_SWFLAGS_SUPERSAMPLEX)
	{
        ps3DRegs[D3DM_SW3DREG_SCALERCTL].ui32RegVal |= MBX1_SCALERCTL_HSCALE;
        psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal    |= MBX1_TACONFIG_SUPERSAMPLEX;
        
        dwWidth *= 2;
	}

	/*
		super sample in Y?
	*/
	if	(psContext->dwFlags & D3DM_CONTEXT_SWFLAGS_SUPERSAMPLEY)
	{
		ps3DRegs[D3DM_SW3DREG_SCALERCTL].ui32RegVal |= MBX1_SCALERCTL_VSCALE;
		psTARegs[D3DM_SWTAREG_CONFIG].ui32RegVal    |= MBX1_TACONFIG_SUPERSAMPLEY;

		dwHeight *= 2;
	}

	/*
		Setup Render min/max pixel clip area to cover the whole render-target

		NB:	Pixel ranges here include the MIN/MAX rectangle edges
	*/
	ps3DRegs[D3DM_SW3DREG_FBXCLIP].ui32RegVal = ((dwWidth - 1) << MBX1_FBXCLIPMAXSHIFT) &
											  (~MBX1_FBXCLIPMAXCLR);
	ps3DRegs[D3DM_SW3DREG_FBYCLIP].ui32RegVal = ((dwHeight - 1) << MBX1_FBYCLIPMAXSHIFT) &
											  (~MBX1_FBYCLIPMAXCLR);

	/*
		Setup TA clip registers to cover the whole render-target

		NB:	Pixel ranges here are upto, but not inclusive of XMAX/YMAX
	*/
	psTARegs[D3DM_SWTAREG_XCLIP].ui32RegVal = (dwWidth << MBX1_TA_XCLIPMAXSHIFT) &
											(~MBX1_TA_XCLIPMAXCLR);