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📄 tsstate.c

📁 Lido PXA270平台开发板的最新BSP,包括源代码
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/******************************************************************************
<module>
* Name         : TSState.c
* Title        : Text Stage State functions
* Author(s)    : Imagination Technologies
* Created      : 2 March 2004
*
* Copyright    : 2004 by Imagination Technologies Limited.
*                All rights reserved.  No part of this software, either
*                material or conceptual may be copied or distributed,
*                transmitted, transcribed, stored in a retrieval system
*                or translated into any human or computer language in any
*                form by any means, electronic, mechanical, manual or
*                other-wise, or disclosed to third parties without the
*                express written permission of Imagination Technologies
*                Limited, Unit 8, HomePark Industrial Estate,
*                King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description  : Entry Points for D3DMobile context callback functions.
*
* Platform     : Windows CE
*
 Modifications	:

 $Log: tsstate.c $
********************************************************************************/

#include "context.h"

/*
	Pixel offset to a mipmap-level within a square maximum-sized mipmap
	(used by AdjustForMaxMipLevel)
*/
static DWORD pdwSquareOffset[] =
{
	0,
	(2048*2048),
	(2048*2048) + (1024*1024),
	(2048*2048) + (1024*1024) + (512*512),
	(2048*2048) + (1024*1024) + (512*512) + (256*256),		
	(2048*2048) + (1024*1024) + (512*512) + (256*256) + (128*128),
	(2048*2048) + (1024*1024) + (512*512) + (256*256) + (128*128) + 4096,
	(2048*2048) + (1024*1024) + (512*512) + (256*256) + (128*128) + 4096 + 1024,
	(2048*2048) + (1024*1024) + (512*512) + (256*256) + (128*128) + 4096 + 1024 + 256 /* we can't go below 8x8 so clamp */
};

/*
	Lookup table for translating D3DMIPMAPLODBIAS value to
	the nearest value we can support.

	The value of index gives the 4-bit fixed point value for the
	Mipmap D-Adjust bits in the TSP control word
	N.B. the range of D3D values is -1.0 to +1.0
	- the whole MBX1 range of -1.75 to +2.0 is
	included for completeness
*/
#define MBX1_MIPLODBIAS_ZEROVALUEENTRY	7

static float fD3DMipLODBiasTrans[] = 
{	 
	-1.75f,	
	-1.5f,  
	-1.25f,  

	-1.0f,	 
	-0.75f,	 
	-0.5f,	 
	-0.25f,	 

	0.0f,	 

	0.25f,	 
	0.5f,	 
	0.75f,	 
	1.0f,	 

	1.25f,	 
	1.5f,	
	1.75f,	 
	2.0f	
};
static DWORD dwColourArgTrans[] =
{
	/*
		Normal - no PVR_COLOURARGTRANS_xxx flags set
	*/
	PVR_COLOURSOURCE_DIFFUSE,
	PVR_COLOURSOURCE_CURRENT,
	PVR_COLOURSOURCE_TEXTURE,
	PVR_COLOURSOURCE_FACTOR,

	PVR_COLOURSOURCE_INVDIFFUSE,
	PVR_COLOURSOURCE_INVCURRENT,
	PVR_COLOURSOURCE_INVTEXTURE,
	PVR_COLOURSOURCE_INVFACTOR,

	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_ONE,
	PVR_COLOURSOURCE_ZERO,

	PVR_COLOURSOURCE_ZERO,
	PVR_COLOURSOURCE_ONE,
	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	/*
		Complement - PVR_COLOURARGTRANS_COMPLEMENT set
	*/
	PVR_COLOURSOURCE_INVDIFFUSE,
	PVR_COLOURSOURCE_INVCURRENT,
	PVR_COLOURSOURCE_INVTEXTURE,
	PVR_COLOURSOURCE_INVFACTOR,

	PVR_COLOURSOURCE_DIFFUSE,
	PVR_COLOURSOURCE_CURRENT,
	PVR_COLOURSOURCE_TEXTURE,
	PVR_COLOURSOURCE_FACTOR,

	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_ZERO,
	PVR_COLOURSOURCE_ONE,

	PVR_COLOURSOURCE_ONE,
	PVR_COLOURSOURCE_ZERO,
	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	/*
		Alpha replicate - PVR_COLOURARGTRANS_ALPHAREPLICATE set
	*/
	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_ONE,
	PVR_COLOURSOURCE_ZERO,

	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	/*
		Complement alpha replicate - PVR_COLOURARGTRANS_ALPHAREPLICATE and 
		PVR_COLOURARGTRANS_COMPLEMENT set
	*/
	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_INVDIFFUSEALPHA,
	PVR_COLOURSOURCE_INVCURRENTALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	PVR_COLOURSOURCE_INVFACTORALPHA,

	PVR_COLOURSOURCE_DIFFUSEALPHA,
	PVR_COLOURSOURCE_CURRENTALPHA,
	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_FACTORALPHA,

	PVR_COLOURSOURCE_ZERO,
	PVR_COLOURSOURCE_ONE,

	PVR_COLOURSOURCE_TEXTUREALPHA,
	PVR_COLOURSOURCE_INVTEXTUREALPHA,
	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};

/*
	Mapping of input alpha arguments (and variants thereof) to their
	corresponding HW alpha source codes (listed above)
*/
#define PVR_ALPHAARGTRANS_ARGMASK				0x0F
#define PVR_ALPHAARGTRANS_COMPLEMENT			0x10

static DWORD dwAlphaArgTrans[] = 
{
	/*
		Normal - no PVR_ALPHAARGTRANS flags set
	*/
	PVR_ALPHASOURCE_DIFFUSEALPHA,
	PVR_ALPHASOURCE_CURRENTALPHA,
	PVR_ALPHASOURCE_TEXTUREALPHA,
	PVR_ALPHASOURCE_FACTORALPHA,

	PVR_ALPHASOURCE_INVDIFFUSEALPHA,
	PVR_ALPHASOURCE_INVCURRENTALPHA,
	PVR_ALPHASOURCE_INVTEXTUREALPHA,
	PVR_ALPHASOURCE_INVFACTORALPHA,

	PVR_ALPHASOURCE_ONE,
	PVR_ALPHASOURCE_ZERO,
	0, 0, 0, 0, 0, 0,

	/*
		Complement - PVR_ALPHAARGTRANS_COMPLEMENT set
	*/
	PVR_ALPHASOURCE_INVDIFFUSEALPHA,
	PVR_ALPHASOURCE_INVCURRENTALPHA,
	PVR_ALPHASOURCE_INVTEXTUREALPHA,
	PVR_ALPHASOURCE_INVFACTORALPHA,

	PVR_ALPHASOURCE_DIFFUSEALPHA,
	PVR_ALPHASOURCE_CURRENTALPHA,
	PVR_ALPHASOURCE_TEXTUREALPHA,
	PVR_ALPHASOURCE_FACTORALPHA,

	PVR_ALPHASOURCE_ZERO,
	PVR_ALPHASOURCE_ONE,
	0, 0, 0, 0, 0, 0
};

/*
	Mapping of HW colour source codes to HW CS1 control (in TSPLCtl3)
*/
static DWORD dwCS1ColourSourceTransLCtl3[] = 
{
	0,													/* COLOURSOURCE_DIFFUSE */
	MBX1_TSPPL3_CS1SELCURRENT,							/* COLOURSOURCE_CURRENT */
	MBX1_TSPPL3_CS1SELTEXTURE,							/* COLOURSOURCE_TEXTURE */
	MBX1_TSPPL3_CS1SELFACTOR,							/* COLOURSOURCE_FACTOR  */

	0,													/* COLOURSOURCE_INVDIFFUSE */
	MBX1_TSPPL3_CS1SELCURRENT | MBX1_TSPPL3_INVCS1,		/* COLOURSOURCE_INVCURRENT */
	MBX1_TSPPL3_CS1SELTEXTURE | MBX1_TSPPL3_INVCS1,		/* COLOURSOURCE_INVTEXTURE */
	MBX1_TSPPL3_CS1SELFACTOR  | MBX1_TSPPL3_INVCS1,		/* COLOURSOURCE_INVFACTOR  */

	0,													/* COLOURSOURCE_DIFFUSEALPHA */
	0,													/* COLOURSOURCE_CURRENTALPHA */
	0,													/* COLOURSOURCE_TEXTUREALPHA */
	0,													/* COLOURSOURCE_FACTORALPHA	 */

	0,													/* COLOURSOURCE_INVDIFFUSEALPHA */
	0,													/* COLOURSOURCE_INVCURRENTALPHA */
	0,													/* COLOURSOURCE_INVTEXTUREALPHA */
	0,													/* COLOURSOURCE_INVFACTORALPHA  */

	MBX1_TSPPL3_CS1SELONE,								/* COLOURSOURCE_ONE	   */
	MBX1_TSPPL3_CS1SELONE | MBX1_TSPPL3_INVCS1,			/* COLOURSOURCE_ZERO   */
	MBX1_TSPPL3_CS1SELFACTOR,							/* COLOURSOURCE_ANY	   */
	MBX1_TSPPL3_CS1SELFACTOR | MBX1_TSPPL3_INVCS1		/* COLOURSOURCE_INVANY */
};

/*
	Mapping of colour source codes to HW CS2 control (in TSPLCtl3)
*/
static DWORD dwCS2ColourSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_CS2SELDIFFUSE,
	MBX1_TSPPL3_CS2SELCURRENT,
	MBX1_TSPPL3_CS2SELTEXTURE,
	MBX1_TSPPL3_CS2SELFACTOR,

	MBX1_TSPPL3_CS2SELDIFFUSE | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELCURRENT | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELTEXTURE | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELFACTOR | MBX1_TSPPL3_INVCS2,

	MBX1_TSPPL3_CS2SELDIFFUSEALPHA,
	MBX1_TSPPL3_CS2SELCURRENTALPHA,
	MBX1_TSPPL3_CS2SELTEXTUREALPHA,
	MBX1_TSPPL3_CS2SELFACTORALPHA,

	MBX1_TSPPL3_CS2SELDIFFUSEALPHA | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELCURRENTALPHA | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELTEXTUREALPHA | MBX1_TSPPL3_INVCS2,
	MBX1_TSPPL3_CS2SELFACTORALPHA | MBX1_TSPPL3_INVCS2,

	0,	/* COLOURSOURCE_ONE	*/
	0,	/* COLOURSOURCE_ZERO */
	MBX1_TSPPL3_CS2SELDIFFUSE,
	MBX1_TSPPL3_CS2SELDIFFUSE | MBX1_TSPPL3_INVCS2
};

/*
	Mapping of colour source codes to HW CS3 control (in TSPLCtl3)
*/
static DWORD dwCS3ColourSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_CS3SELDIFFUSE,
	MBX1_TSPPL3_CS3SELCURRENT,
	MBX1_TSPPL3_CS3SELTEXTURE,
	0,	/* COLOURSOURCE_FACTOR */

	MBX1_TSPPL3_CS3SELDIFFUSE | MBX1_TSPPL3_INVCS3,
	MBX1_TSPPL3_CS3SELCURRENT | MBX1_TSPPL3_INVCS3,
	MBX1_TSPPL3_CS3SELTEXTURE | MBX1_TSPPL3_INVCS3,
	0,

	0,
	0,
	0,
	0,

	0,
	0,
	0,
	0,

	MBX1_TSPPL3_CS3SELONE,
	MBX1_TSPPL3_CS3SELONE | MBX1_TSPPL3_INVCS3,
	MBX1_TSPPL3_CS3SELDIFFUSE,
	MBX1_TSPPL3_CS3SELDIFFUSE | MBX1_TSPPL3_INVCS3
};

/*
	Mapping of colour source codes to HW CS4 control (in TSPLCtl3)
*/
static DWORD dwCS4ColourSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_CS4SELDIFFUSE,
	MBX1_TSPPL3_CS4SELCURRENT,
	MBX1_TSPPL3_CS4SELTEXTURE,
	MBX1_TSPPL3_CS4SELFACTOR,

	MBX1_TSPPL3_CS4SELDIFFUSE | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELCURRENT | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELTEXTURE | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELFACTOR | MBX1_TSPPL3_INVCS4,

	MBX1_TSPPL3_CS4SELDIFFUSEALPHA,
	MBX1_TSPPL3_CS4SELCURRENTALPHA,
	MBX1_TSPPL3_CS4SELTEXTUREALPHA,
	MBX1_TSPPL3_CS4SELFACTORALPHA,

	MBX1_TSPPL3_CS4SELDIFFUSEALPHA | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELCURRENTALPHA | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELTEXTUREALPHA | MBX1_TSPPL3_INVCS4,
	MBX1_TSPPL3_CS4SELFACTORALPHA | MBX1_TSPPL3_INVCS4,

	0,	/* COLOURSOURCE_ONE  */
	0,	/* COLOURSOURCE_ZERO */
	MBX1_TSPPL3_CS4SELDIFFUSE,
	MBX1_TSPPL3_CS4SELDIFFUSE | MBX1_TSPPL3_INVCS4
};

/*
	Mapping of alpha source codes to HW AS1 control (in TSPLLCtl3)
*/
static DWORD dwAS1AlphaSourceTransLCtl3[] = 
{
	0,													 /* ALPHASOURCE_DIFFUSEALPHA */
	MBX1_TSPPL3_AS1SELCURRENTALPHA,						 /* ALPHASOURCE_CURRENTALPHA */
	MBX1_TSPPL3_AS1SELTEXTUREALPHA,						 /* ALPHASOURCE_TEXTUREALPHA */
	MBX1_TSPPL3_AS1SELDIFFUSEALPHA,						 /* ALPHASOURCE_FACTORALPHA  */

	0,													 /* ALPHASOURCE_INVDIFFUSEALPHA */
	MBX1_TSPPL3_AS1SELCURRENTALPHA | MBX1_TSPPL3_INVAS1, /* ALPHASOURCE_INVCURRENTALPHA */
	MBX1_TSPPL3_AS1SELTEXTUREALPHA | MBX1_TSPPL3_INVAS1, /* ALPHASOURCE_INVTEXTUREALPHA */
	MBX1_TSPPL3_AS1SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS1,	 /* ALPHASOURCE_INVFACTORALPHA  */

	MBX1_TSPPL3_AS1SELONE,								 /* ALPHASOURCE_ONE    */
	MBX1_TSPPL3_AS1SELONE | MBX1_TSPPL3_INVAS1,			 /* ALPHASOURCE_ZERO   */
	MBX1_TSPPL3_AS1SELDIFFUSEALPHA,						 /* ALPHASOURCE_ANY    */
	MBX1_TSPPL3_AS1SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS1	 /* ALPHASOURCE_INVANY */
};

/*
	Mapping of alpha source codes to HW AS2 control (in TSPLLCtl3)
*/
static DWORD dwAS2AlphaSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_AS2SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS2SELCURRENTALPHA,
	MBX1_TSPPL3_AS2SELTEXTUREALPHA,
	MBX1_TSPPL3_AS2SELFACTORALPHA,

	MBX1_TSPPL3_AS2SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS2,
	MBX1_TSPPL3_AS2SELCURRENTALPHA | MBX1_TSPPL3_INVAS2,
	MBX1_TSPPL3_AS2SELTEXTUREALPHA | MBX1_TSPPL3_INVAS2,
	MBX1_TSPPL3_AS2SELFACTORALPHA | MBX1_TSPPL3_INVAS2,

	0,	/* ALPHASOURCE_ONE  */
	0,	/* ALPHASOURCE_ZERO */
	MBX1_TSPPL3_AS2SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS2SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS2
};

/*
	Mapping of alpha source codes to HW AS3 control (in TSPLLCtl3)
*/
static DWORD dwAS3AlphaSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_AS3SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS3SELCURRENTALPHA,
	MBX1_TSPPL3_AS3SELTEXTUREALPHA,
	0,	/* ALPHASOURCE_INVFACTORALPHA */

	MBX1_TSPPL3_AS3SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS3,
	MBX1_TSPPL3_AS3SELCURRENTALPHA | MBX1_TSPPL3_INVAS3,
	MBX1_TSPPL3_AS3SELTEXTUREALPHA | MBX1_TSPPL3_INVAS3,
	0,	/* ALPHASOURCE_INVFACTORALPHA */

	MBX1_TSPPL3_AS3SELONE,
	MBX1_TSPPL3_AS3SELONE | MBX1_TSPPL3_INVAS3,
	MBX1_TSPPL3_AS3SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS3SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS3
};

/*
	Mapping of alpha source codes to HW AS4 control (in TSPLLCtl3)
*/
static DWORD dwAS4AlphaSourceTransLCtl3[] = 
{
	MBX1_TSPPL3_AS4SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS4SELCURRENTALPHA,
	MBX1_TSPPL3_AS4SELTEXTUREALPHA,
	MBX1_TSPPL3_AS4SELFACTORALPHA,

	MBX1_TSPPL3_AS4SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS4,
	MBX1_TSPPL3_AS4SELCURRENTALPHA | MBX1_TSPPL3_INVAS4,
	MBX1_TSPPL3_AS4SELTEXTUREALPHA | MBX1_TSPPL3_INVAS4,
	MBX1_TSPPL3_AS4SELFACTORALPHA | MBX1_TSPPL3_INVAS4,

	0, /* ALPHASOURCE_ONE  */
	0, /* ALPHASOURCE_ZERO */
	MBX1_TSPPL3_AS4SELDIFFUSEALPHA,
	MBX1_TSPPL3_AS4SELDIFFUSEALPHA | MBX1_TSPPL3_INVAS4
};

/*
	Source permutation table, representing different ways to map required
	sources for an OP onto the four HW sources (CS1-4 / AS1-4).

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