pdptimings.cpp

Lido PXA270平台开发板的最新BSP,包括源代码

/**************************************************************************
 Name         : pdptimings.cpp
 Title        : PDP Timing Generation
 Author       : Paul Buxton
 Created      : 7 January 2003

 Copyright    : 2002 by Imaginationc Technologies Limited. All rights reserved.
              : No part of this software, either material or conceptual 
              : may be copied or distributed, transmitted, transcribed,
              : stored in a retrieval system or translated into any 
              : human or computer language in any form by any means,
              : electronic, mechanical, manual or other-wise, or 
              : disclosed to third parties without the express written
              : permission of Imagination Technologies Limited, Unit 8, HomePark
              : Industrial Estate, King's Langley, Hertfordshire,
              : WD4 8LZ, U.K.

 Description  : Timing Generation Functions

 Platform     : WinCE
 Version	  : $Revision: 1.7 $
 Modifications	: 
 $Log: pdptimings.cpp $

  --- Revision Logs Removed --- 

  --- Revision Logs Removed --- 

  --- Revision Logs Removed --- 

  --- Revision Logs Removed --- 

  --- Revision Logs Removed --- 

  --- Revision Logs Removed --- 
 **************************************************************************/

#include <windows.h>

extern "C"
{
	#include "services_headers.h"

	#include "pdpal.h"
	#include "pdptimings.h"
}

// Local Functions
PDP_ERROR GetCVT(WORD wXRes,WORD wYRes,WORD wRefreshRate,BOOL  bIsReduced,PPDP_TIMINGS psTiming);
PDP_ERROR FindTiming(WORD wXRes,WORD wYRes,WORD wRefreshRate,PPDP_TIMINGS psTiming,PPDP_TIMINGS asTimings,int nSize);
PDP_ERROR ConstructEnumTable(PPDP_TIMINGS asTimings,int nSize,PPDP_EnumerateModesList psModeList);


#ifdef SUPPORT_MARATHON_DEVICE
// LCD switch configuration settings

//PDP_SHARP_LQ057Q3DC02:				
//PDP_SHARP_LLT1820H				DVI  			
//PDP_TOSHIBA_LTM04C380S:  			



//PDP_SHARP_LS047D
//PDP_SHARP_LQ022B2DB02T
//PDP_EPSON_LD22002TB301

//SYS_LCD_CONFIG sLCDConfigDefault = {SYS_FALLING,SYS_FALLING,SYS_FALLING,SYS_FALLING,IMG_TRUE,SYS_3MA,SYS_3MA,SYS_SOURCE_PDP};
SYS_LCD_CONFIG sLCDConfigDefault =    {SYS_FALLING,SYS_FALLING,SYS_FALLING,SYS_FALLING,IMG_TRUE,SYS_6MA_10MA,SYS_6MA_10MA,SYS_SOURCE_PDP};
SYS_LCD_CONFIG sLCDConfigVGA = 	      {SYS_RISING,SYS_RISING,SYS_RISING,SYS_RISING,IMG_TRUE,SYS_3MA,SYS_3MA,SYS_SOURCE_PDP};
SYS_LCD_CONFIG sLCDConfigLTM04C380S = {SYS_FALLING,SYS_FALLING,SYS_FALLING,SYS_FALLING,IMG_TRUE,SYS_3MA,SYS_3MA,SYS_SOURCE_PDP};
SYS_LCD_CONFIG sLCDConfigSharpLQ022 = {SYS_RISING,SYS_RISING,SYS_RISING,SYS_RISING,IMG_TRUE,SYS_3MA,SYS_3MA,SYS_SOURCE_PDP};

#endif



// Discrete Monitor Timings, for use on the CEPC System using a kyro card
PDP_TIMINGS asDMTTimings[]=
{
	{
		640,							// XRes
		480,							// Yres
		60,								// Refresh rate in Hz.
		31469,                       	// Line rate in Hz (typically >30KHz, on vga timings
		25175000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		8,								// Horizontal front porch
		96,								// Horiztonal sync
		40,								// Horizontal back porch
		8,								// Horizontal left border
		8,								// Horizontal right border
		2,								// Vertical front porch
		2,								// Vertical sync
		25,								// Veritcal back porch
		8,								// Vertical top border
		8,								// Vertical bottom border
		640,							// HActive
		480,							// VActive
										
		1,								// Polarity of Hsync pulse, True = Positive;
		1,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{   /* Bordered portrait 480 x 640 image displayed using 1024 x 768 timings. */
		480,							// XRes
		640,							// Yres
		60,								// Refresh rate in Hz.
		48363,                       	// Line rate in Hz (typically >30KHz, on vga timings
		65000000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		24,								// Horizontal front porch
		136,							// Horiztonal sync
		160,							// Horizontal back porch
		272,								// Horizontal left border
		272,								// Horizontal right border
		3,								// Vertical front porch
		6,								// Vertical sync
		29,								// Veritcal back porch
		64,								// Vertical top border
		64,								// Vertical bottom border
		480,							// XRes
		640,							// Yres
										
		1,								// Polarity of Hsync pulse, True = Positive;
		1,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{
		800,							// XRes
		600,							// Yres
		60,								// Refresh rate in Hz.
		37879,                       	// Line rate in Hz (typically >30KHz, on vga timings
		40000000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		40,								// Horizontal front porch
		128,							// Horiztonal sync
		88,								// Horizontal back porch
		0,								// Horizontal left border
		0,								// Horizontal right border
		1,								// Vertical front porch
		4,								// Vertical sync
		23,								// Veritcal back porch
		0,								// Vertical top border
		0,								// Vertical bottom border
		800,							// XRes
		600,							// Yres
										
		1,								// Polarity of Hsync pulse, True = Positive;
		1,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{
		1024,							// XRes
		768,							// Yres
		60,								// Refresh rate in Hz.
		48363,                       	// Line rate in Hz (typically >30KHz, on vga timings
		65000000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		24,								// Horizontal front porch
		136,							// Horiztonal sync
		160,							// Horizontal back porch
		0,								// Horizontal left border
		0,								// Horizontal right border
		3,								// Vertical front porch
		6,								// Vertical sync
		29,								// Veritcal back porch
		0,								// Vertical top border
		0,								// Vertical bottom border
		1024,							// XRes
		768,							// Yres
										
		1,								// Polarity of Hsync pulse, True = Positive;
		1,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{
		320,							// XRes
		240,							// Yres
		60,								// Refresh rate in Hz.
		31469,                       	// Line rate in Hz (typically >30KHz, on vga timings
		25175000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		TRUE,							// Not Line doubled
		TRUE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		8,								// Horizontal front porch
		96,								// Horiztonal sync
		40,								// Horizontal back porch
		8,								// Horizontal left border
		8,								// Horizontal right border
		2,								// Vertical front porch
		2,								// Vertical sync
		25,								// Veritcal back porch
		8,								// Vertical top border
		8,								// Vertical bottom border
		320,							// XRes
		240,							// Yres
										
		0,								// Polarity of Hsync pulse, True = Positive;
		0,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{
		240,							// XRes
		320,							// Yres
		60,								// Refresh rate in Hz.
		31469,                       	// Line rate in Hz (typically >30KHz, on vga timings
		25175000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		8,								// Horizontal front porch
		96,								// Horiztonal sync
		40,								// Horizontal back porch
		208,							// Horizontal left border
		208,							// Horizontal right border
		2,								// Vertical front porch
		2,								// Vertical sync
		25,								// Veritcal back porch
		88,								// Vertical top border
		88,								// Vertical bottom border
		240,							// Xres
		320,							// YRes
										
		0,								// Polarity of Hsync pulse, True = Positive;
		0,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	},
	{
		1280,							// XRes
		1024,							// Yres
		60,								// Refresh rate in Hz.
		63981,                       	// Line rate in Hz (typically b>30KHz, on vga timings
		108000000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		48,								// Horizontal front porch
		112,							// Horiztonal sync
		248,							// Horizontal back porch
		0,								// Horizontal left border
		0,								// Horizontal right border
		1,								// Vertical front porch
		3,								// Vertical sync
		38,								// Veritcal back porch
		0,								// Vertical top border
		0,								// Vertical bottom border
		1280,							// XRes
		1024,							// Yres
										
		1,								// Polarity of Hsync pulse, True = Positive;
		1,								// Polarity of VSync pulse, True = Positive;
		PDP_FULL_REFRESH,				// Specify we refresh the screen at full rate
		0,								// No time between refreshes (not used in PDP_FULL_REFRESH mode
		TRUE,							// Full rate Syncs
		TRUE,							// Full rate interrupts
		10000,							// Backlight control value of 10us which equates to a 100Khz Backlight frequency
	}
};



// Timings for the Sharp LCD Panel
PDP_TIMINGS asLQ057Q3DC02Timings[]=
{
	{	// These are the timings for the Sharp LCD Display panel.
		320,							// XRes
		240,							// Yres
		60,								// Refresh rate in Hz.
		14840,                       	// Line rate in Hz (typically >30KHz, on vga timings
		6530000,						// Dot Clock in Hz (typically >27 MHz, on vga timings

		FALSE,							// Not Line doubled
		FALSE,							// Not pixel doubled
		TRUE,							// Blanking signal is positive

		1,								// Horizontal front porch
		68,								// Horiztonal sync
		51,								// Horizontal back porch
		0,								// Horizontal left border
		0,								// Horizontal right border
		6,								// Vertical front porch
		5,								// Vertical sync
		2,								// Veritcal back porch
		0,								// Vertical top border
		0,								// Vertical bottom border
		320,							// HActive
		240,							// VActive