pdptimings.h

Lido PXA270平台开发板的最新BSP,包括源代码

/**************************************************************************
 Name         : pdptimings.h
 Title        : pdp timings 
 Author       : Paul Buxton
 Created      : 30 October 2002

 Copyright    : 2002 by Imaginationc Technologies Limited. All rights reserved.
              : No part of this software, either material or conceptual 
              : may be copied or distributed, transmitted, transcribed,
              : stored in a retrieval system or translated into any 
              : human or computer language in any form by any means,
              : electronic, mechanical, manual or other-wise, or 
              : disclosed to third parties without the express written
              : permission of Imagination Technologies Limited, Unit 8, HomePark
              : Industrial Estate, King's Langley, Hertfordshire,
              : WD4 8LZ, U.K.

 Description  : pdp timing functions

 Platform     : WinCE
 Version	  : $Revision: 1.3 $
 Modifications	: 
 $Log: pdptimings.h $

  --- Revision Logs Removed --- 
 **************************************************************************/

#ifndef _PDPTIMINGS_
#define _PDPTIMINGS_

#include "pdpal.h"


typedef		enum	_PDP_TIMINGSELECT_
{
	PDP_CVT=0x0,
	PDP_CVT_REDUCED,
	PDP_DMT,
	PDP_SHARP_LQ057Q3DC02,				// Default Display used on FPGA Systems 320x240 Native
	PDP_SHARP_LQ022B2DB02T,				// Mobile Phone Style display 176x220
	PDP_TOSHIBA_LTM04C380S,				// Toshbiba Display used in Mainstone Systems 640x480
	PDP_SHARP_LLT1820H,					// DVI Flat Panel Monitor	640x480 -> 1280x1024
	PDP_SHARP_LS047D,					// Sharp prototype panel 640x480
	PDP_EPSON_LD22002TB301				// Epson Stinger panel

} PDP_TIMINGSELECT,*PPDP_TIMINGSELECT;


/* Display timings */
typedef struct _PDP_TIMINGS
{
	WORD	wXRes;						// 
	WORD	wYRes;
	WORD	wRefreshHz;					// Refresh rate in Hz.
	DWORD	dwLineHz;					// Line rate in Hz (typically >30KHz, on vga timings
	DWORD	dwClockHz;					// Dot Clock in Hz (typically >27 MHz, on vga timings
	BOOL 	bLineDouble;				// This is a line doubled mode 
	BOOL 	bPixelDouble;				// This is a pixel doubled mode.
	BOOL	bBlankingPositive;			// Blanking signal is positive

	WORD	wHFP;						// Horizontal front porch
	WORD	wHSync;						// Horiztonal sync
	WORD	wHBP;						// Horizontal back porch
	WORD	wHLB;						// Horizontal left border
	WORD	wHRB;						// Horizontal right border
	WORD	wVFP;						// Vertical front porch
	WORD	wVSync;						// Vertical sync
	WORD	wVBP;						// Veritcal back porch
	WORD	wVTB;						// Vertical top border
	WORD	wVBB;						// Vertical bottom border
	WORD	wHActive;   				// HActive 
	WORD	wVActive;					// VSctive
	
	BOOL	bHSync;						// Polarity of Hsync pulse, True = Positive;
	BOOL	bVSync; 					// Polarity of VSync pulse, True = Positive;

	PDP_DISPLAY_UPDATE	eDisplayUpdate;	// Display update frequency type;
	WORD	wUpdateWait;				// Number of frames between updates when in reduced mode.
	BOOL	bFullRateSyncs;				// Generate Syncs at Full timing rate or reduced rate.
	BOOL	bFullRateInterrupts;		// Generate interrupts at Full timing rate or reduced timing rate.
	DWORD	dwBacklightPeriod;			// The period of one backlight PWM clock in ns (should be between 77ns and 5 ms)

}PDP_TIMINGS,*PPDP_TIMINGS;




PDP_ERROR TimingsToRelative(PPDP_TIMINGS psTiming ,PPDP_RELATIVETIMES psRelative);
PDP_ERROR GetModeTimings(WORD wXRes,WORD wYRes,WORD wRefreshRate,PDP_TIMINGSELECT eMethod,PPDP_TIMINGS psTiming);
PDP_ERROR PDPConstructModeTable(PDP_TIMINGSELECT eMethod,PPDP_EnumerateModesList psModeEnum);

#ifdef SUPPORT_MARATHON_DEVICE
PDP_ERROR GetLCDSwitchConfig(PDP_TIMINGSELECT eMethod, PSYS_LCD_CONFIG pLCDSwitchConfig);
#endif


#endif /* #ifndef _PDPTIMINGS_ */
/*****************************************************************************
 End of file (PDPTIMINGS.H)
*****************************************************************************/