📄 dp_hardware_marathon.c
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0, (0x5D<<SLOT_SIZE), 0, 0x00FFFFFF, /* Field 1 - Background colour */
0, (0x5C<<SLOT_SIZE), 0, 0x00FFFFFF, /* Field 2 - Border colour */
0, (0x54<<SLOT_SIZE), 0, 0x00ffFFFF, /* Field 3 - Write data to palette */
0, (0x54<<SLOT_SIZE), 24, 0xFF000000, /* Field 4 - Palette entry number */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 5 - Which plane is the palette data for ? */
0, (0x55<<SLOT_SIZE), 31, 0x80000000, /* Field 6 - Control : Sync active */
0, (0x55<<SLOT_SIZE), 29, 0x20000000, /* Field 7 - Control : Software reset */
0, (0x55<<SLOT_SIZE), 28, 0x10000000, /* Field 8 - Control : Power down mode */
0, (0xC3<<SLOT_SIZE), 0, 0x00000001, /* Field 9 - Control : List loader update control */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 10 - Control : Field polarity */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 11 - Control : Interlace enabled */
0, (0x55<<SLOT_SIZE), 7, 0x00000080, /* Field 12 - Control : VSYNC slave */
0, (0x55<<SLOT_SIZE), 6, 0x00000040, /* Field 13 - Control : HSYNC slave */
0, (0x55<<SLOT_SIZE), 5, 0x00000020, /* Field 14 - Control : Blanking polarity */
0, (0x55<<SLOT_SIZE), 4, 0x00000010, /* Field 15 - Control : Blank disable */
0, (0x55<<SLOT_SIZE), 3, 0x00000008, /* Field 16 - Control : VSYNC polarity */
0, (0x55<<SLOT_SIZE), 2, 0x00000004, /* Field 17 - Control : VSYNC disable */
0, (0x55<<SLOT_SIZE), 1, 0x00000002, /* Field 18 - Control : HSYNC polarity */
0, (0x55<<SLOT_SIZE), 0, 0x00000001, /* Field 19 - Control : HSYNC disable */
0, (0x59<<SLOT_SIZE), 0, 0x00000FFF, /* Field 20 - Timing : Vertical total */
0, (0x5B<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 21 - Timing : Vertical front porch start */
0, (0x59<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 22 - Timing : Vertical back porch start */
0, (0x5A<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 23 - Timing : Vertical active start */
0, (0x5A<<SLOT_SIZE), 0, 0x00000FFF, /* Field 24 - Timing : Vertical top border start */
0, (0x5B<<SLOT_SIZE), 0, 0x00000FFF, /* Field 25 - Timing : Vertical bottom border start */
0, (0x56<<SLOT_SIZE), 0, 0x00000FFF, /* Field 26 - Timing : Horizontal total */
0, (0x58<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 27 - Timing : Horizontal front porch start */
0, (0x56<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 28 - Timing : Horizontal back porch start */
0, (0x57<<SLOT_SIZE), 16, 0x0FFF0000, /* Field 29 - Timing : Horizontal active start */
0, (0x57<<SLOT_SIZE), 0, 0x00000FFF, /* Field 30 - Timing : Horizontal left border start */
0, (0x58<<SLOT_SIZE), 0, 0x00000FFF, /* Field 31 - Timing : Horizontal right border start */
4, (0xC1<<SLOT_SIZE), 0, 0x007FFFFF, /* Field 32 - Dispatcher pending addr. */
4, (0xC0<<SLOT_SIZE), 0, 0x007FFFFF, /* Field 33 - Dispatcher status addr. */
0, (0xC0<<SLOT_SIZE), 23, 0x00800000, /* Field 34 - Dispatcher status flag */
0, (0xC1<<SLOT_SIZE), 24, 0xFF000000, /* Field 35 - Length of pending buffer */
0, (0xC1<<SLOT_SIZE), 23, 0x00800000, /* Field 36 - Pending address valid flag */
0, (0x80<<SLOT_SIZE), 0, 0xFFFFFFFF, /* Field 37 - Base address and access model for video */
/* gamma correction table */
0, (0x94<<SLOT_SIZE), 0, 0x00FFFFFF, /* Field 38 - Base address and access model for */
/* graphics gamma correction table */
0, (0x62<<SLOT_SIZE), 30, 0xC0000000, /* Field 39 - Memory interface : Refresh period */
0, (0x62<<SLOT_SIZE), 0, 0x0000003F, /* Field 40 - Memory interface : Burst length */
0, (0x62<<SLOT_SIZE), 8, 0x00007F00, /* Field 41 - Memory interface : Threshold */
0, (0x62<<SLOT_SIZE), 16, 0x007F0000, /* Field 42 - Memory interface : Y Threshold */
0, (0x62<<SLOT_SIZE), 24, 0x7F000000, /* Field 43 - Memory interface : UV Threshold */
0, (0x64<<SLOT_SIZE), 27, 0x08000000, /* Field 44 - Memory interface : Vertical scaler underrun control */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 45 - Interrupt status : Cursor 2 underrun */
0, (0x5E<<SLOT_SIZE), 10, 0x00000400, /* Field 46 - Interrupt status : Cursor 1 underrun */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 47 - Interrupt status : Plane 6 underrun */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 48 - Interrupt status : Plane 5 underrun */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 49 - Interrupt status : Plane 4 underrun */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 50 - Interrupt status : Plane 3 underrun */
DP_NO_REG, DP_NO_REG, DP_NO_REG, DP_NO_REG, /* Field 51 - Interrupt status : Plane 2 underrun */
0, (0x5E<<SLOT_SIZE), 4, 0x00000010, /* Field 52 - Interrupt status : Plane 1 underrun */
0, (0x5E<<SLOT_SIZE), 17, 0x00020000, /* Field 53 - Interrupt status : Plane 2 buffer overrun */
0, (0x5E<<SLOT_SIZE), 16, 0x00010000, /* Field 54 - Interrupt status : Plane 1 buffer overrun */
0, (0x5E<<SLOT_SIZE), 3, 0x00000008, /* Field 55 - Interrupt status : Vertical blanking - field 2 */
0, (0x5E<<SLOT_SIZE), 2, 0x00000004, /* Field 56 - Interrupt status : Vertical blanking - field 1 */
0, (0x5E<<SLOT_SIZE), 1, 0x00000002, /* Field 57 - Interrupt status : Horizontal blanking - field 2 */
0, (0x5E<<SLOT_SIZE), 0, 0x00000001, /* Field 58 - Interrupt status : Horizontal blanking - field 1 */
0, (0x5F<<SLOT_SIZE), 11, 0x00000800, /* Field 59 - Interrupt enable : Cursor 2 underrun */
0, (0x5F<<SLOT_SIZE), 10, 0x00000400, /* Field 60 - Interrupt enable : Cursor 1 underrun */
0, (0x5F<<SLOT_SIZE), 9, 0x00000200, /* Field 61 - Interrupt enable : Plane 6 underrun */
0, (0x5F<<SLOT_SIZE), 8, 0x00000100, /* Field 62 - Interrupt enable : Plane 5 underrun */
0, (0x5F<<SLOT_SIZE), 7, 0x00000080, /* Field 63 - Interrupt enable : Plane 4 underrun */
0, (0x5F<<SLOT_SIZE), 6, 0x00000040, /* Field 64 - Interrupt enable : Plane 3 underrun */
0, (0x5F<<SLOT_SIZE), 5, 0x00000020, /* Field 65 - Interrupt enable : Plane 2 underrun */
0, (0x5F<<SLOT_SIZE), 4, 0x00000010, /* Field 66 - Interrupt enable : Plane 1 underrun */
0, (0x5F<<SLOT_SIZE), 17, 0x00020000, /* Field 67 - Interrupt status : Plane 2 buffer overrun */
0, (0x5F<<SLOT_SIZE), 16, 0x00010000, /* Field 68 - Interrupt status : Plane 1 buffer overrun */
0, (0x5F<<SLOT_SIZE), 3, 0x00000008, /* Field 69 - Interrupt enable : Vertical blanking - field 2 */
0, (0x5F<<SLOT_SIZE), 2, 0x00000004, /* Field 70 - Interrupt enable : Vertical blanking - field 1 */
0, (0x5F<<SLOT_SIZE), 1, 0x00000002, /* Field 71 - Interrupt enable : Horizontal blanking - field 2 */
0, (0x5F<<SLOT_SIZE), 0, 0x00000001, /* Field 72 - Interrupt enable : Horizontal blanking - field 1 */
0, (0x60<<SLOT_SIZE), 16, 0x00010000, /* Field 73 - Interrupt control : Apply HBLANK on a specific line */
0, (0x60<<SLOT_SIZE), 0, 0x00000FFF, /* Field 74 - Interrupt control : Line to blank on. */
0, (0xC5<<SLOT_SIZE), 0, 0x00000fff, /* Field 75 - Timing : Horizontal Display enable finish */
0, (0xC5<<SLOT_SIZE), 16, 0x0fff0000, /* Field 76 - Timing : Horizontal Display enable start */
0, (0xC6<<SLOT_SIZE), 0, 0x00000fff, /* Field 77 - Timing : Vertical Display enable finish */
0, (0xC6<<SLOT_SIZE), 16, 0x0fff0000, /* Field 78 - Timing : Vertical Display enable start */
0, (0xC4<<SLOT_SIZE), 0, 0x00000fff, /* Field 79 - Timing : Vertical Fetch Start */
0, (0xc4<<SLOT_SIZE), 16, 0x0fff0000, /* Field 80 - Timing : Vertical Event Start */
0, (0x55<<SLOT_SIZE), 26, 0x04000000, /* Field 81 - Control : Display Update Sync control */
0, (0x55<<SLOT_SIZE), 25, 0x02000000, /* Field 82 - Control : Display Update Interrupt Control */
0, (0x55<<SLOT_SIZE), 24, 0x01000000, /* Field 83 - Control : Display Update Control */
0, (0x55<<SLOT_SIZE), 16, 0x000f0000, /* Field 84 - Control : Display Update Wait */
0, (0x55<<SLOT_SIZE), 11, 0x00000800, /* Field 85 - Control : Pixel Clock Polatiry */
0, (0x55<<SLOT_SIZE), 12, 0x00001000, /* Field 86 - Control : Composite Output Enable */
0, (0xC7<<SLOT_SIZE), 0, 0x00ffffff, /* Field 87 - Control : Output Data Mask */
0, (0xC7<<SLOT_SIZE), 30, 0x40000000, /* Field 88 - Control : Blank Level */
0, (0xC7<<SLOT_SIZE), 31, 0x80000000, /* Field 89 - Control : Mask Level */
0, (0xCC<<SLOT_SIZE), 11, 0x003ff800, /* Field 90 - Color Space U Coeff for R Channel */
0, (0xCC<<SLOT_SIZE), 0, 0x000007ff, /* Field 91 - Color Space Y Coeff for R Channel */
0, (0xCD<<SLOT_SIZE), 11, 0x003ff800, /* Field 92 - Color Space Y Coeff for G Channel */
0, (0xCD<<SLOT_SIZE), 0, 0x000007ff, /* Field 93 - Color Space V Coeff for R Channel */
0, (0xCE<<SLOT_SIZE), 11, 0x003ff800, /* Field 94 - Color Space V Coeff for G Channel */
0, (0xCE<<SLOT_SIZE), 0, 0x000007ff, /* Field 95 - Color Space U Coeff for G Channel */
0, (0xCF<<SLOT_SIZE), 11, 0x003ff800, /* Field 96 - Color Space U Coeff for B Channel */
0, (0xCF<<SLOT_SIZE), 0, 0x000007ff, /* Field 97 - Color Space Y Coeff for B Channel */
0, (0xD0<<SLOT_SIZE), 0, 0x000007ff, /* Field 98 - Color Space V Coeff for B Channel */
};
const DP_Capabilities DP_asStreamCapabilities [ DP_NO_OF_STREAMS ] =
{
/* Graphics */
{
/* Supported colour space conversion modes */
{
DP_TRUE, /* HDTV mode */
DP_TRUE, /* SDTV mode */
DP_TRUE, /* Legacy HDTV mode */
DP_TRUE /* Legacy SDTV mode */
},
/* Supported pixel modes */
{
DP_TRUE, /* 8 bit indexed */
DP_TRUE, /* 4 bit indexed */
DP_TRUE, /* 8 bit indexed, 8 bit alpha */
DP_TRUE, /* 8 bit rgb 322 */
DP_TRUE, /* 12 bit rgb 444, 4 bit alpha */
DP_TRUE, /* 15 bit rgb 555, 1 bit alpha */
DP_TRUE, /* 24 bit rgb 888 */
DP_TRUE, /* 16 bit rgb 565 */
DP_TRUE, /* 24 bit rgb 888, 8 bit alpha */
DP_TRUE, /* 16 bit yuv 420, planar */
DP_TRUE, /* 16 bit yuv 422, uy0vy1 */
DP_TRUE, /* 16 bit yuv 422, vy0uy1 */
DP_TRUE, /* 16 bit yuv 422, y0uy1v */
DP_TRUE /* 16 bit yuv 422, y0vy1u */
},
/* Supported alpha blend modes */
{
DP_TRUE, /* No alpha blending */
DP_TRUE, /* Global alpha blending */
DP_TRUE, /* Per pixel alpha blending */
DP_TRUE /* Pixel Invert */
},
DP_SLAVE_MODE_NO_SLAVE_SUPPORT, /* Slave mode support (enum) */
0x00, /* Slave mode qualifier */
DP_FALSE, /* Plane is a hardware cursor */
DP_FALSE /* Off screen repositioning supported */
},
/* Video */
{
/* Supported colour space conversion modes */
{
DP_TRUE, /* HDTV mode */
DP_TRUE, /* SDTV mode */
DP_TRUE, /* Legacy HDTV mode */
DP_TRUE /* Legacy SDTV mode */
},
/* Supported pixel modes */
{
DP_TRUE, /* 8 bit indexed */
DP_TRUE, /* 4 bit indexed */
DP_TRUE, /* 8 bit indexed, 8 bit alpha */
DP_TRUE, /* 8 bit rgb 322 */
DP_TRUE, /* 12 bit rgb 444, 4 bit alpha */
DP_TRUE, /* 15 bit rgb 555, 1 bit alpha */
DP_TRUE, /* 24 bit rgb 888 */
DP_TRUE, /* 16 bit rgb 565 */
DP_TRUE, /* 24 bit rgb 888, 8 bit alpha */
DP_TRUE, /* 16 bit yuv 420, planar */
DP_TRUE, /* 16 bit yuv 422, uy0vy1 */
DP_TRUE, /* 16 bit yuv 422, vy0uy1 */
DP_TRUE, /* 16 bit yuv 422, y0uy1v */
DP_TRUE /* 16 bit yuv 422, y0vy1u */
},
/* Supported alpha blend modes */
{
DP_TRUE, /* No alpha blending */
DP_TRUE, /* Global alpha blending */
DP_TRUE, /* Per pixel alpha blending */
DP_TRUE /* Pixel Invert */
},
DP_SLAVE_MODE_NO_SLAVE_SUPPORT, /* Slave mode support (enum) */
0x00, /* Slave mode qualifier */
DP_FALSE, /* Plane is a hardware cursor */
DP_FALSE /* Off screen repositioning supported */
},
/* Cursor */
{
/* Supported colour space conversion modes */
{
DP_FALSE, /* HDTV mode */
DP_FALSE, /* SDTV mode */
DP_FALSE, /* Legacy HDTV mode */
DP_FALSE /* Legacy SDTV mode */
},
/* Supported pixel modes */
{
DP_TRUE, /* 8 bit indexed */
DP_TRUE, /* 4 bit indexed */
DP_TRUE, /* 8 bit indexed, 8 bit alpha */
DP_TRUE, /* 8 bit rgb 322 */
DP_TRUE, /* 12 bit rgb 444, 4 bit alpha */
DP_TRUE, /* 15 bit rgb 555, 1 bit alpha */
DP_TRUE, /* 24 bit rgb 888 */
DP_TRUE, /* 16 bit rgb 565 */
DP_TRUE, /* 24 bit rgb 888, 8 bit alpha */
DP_FALSE, /* 16 bit yuv 420, planar */
DP_FALSE, /* 16 bit yuv 422, uy0vy1 */
DP_FALSE, /* 16 bit yuv 422, vy0uy1 */
DP_FALSE, /* 16 bit yuv 422, y0uy1v */
DP_FALSE /* 16 bit yuv 422, y0vy1u */
},
/* Supported alpha blend modes */
{
DP_TRUE, /* No alpha blending */
DP_TRUE, /* Global alpha blending */
DP_TRUE, /* Per pixel alpha blending */
DP_TRUE /* Pixel Invert */
},
DP_SLAVE_MODE_NO_SLAVE_SUPPORT, /* Slave mode support (enum) */
0x00, /* Slave mode qualifier */
DP_TRUE, /* Plane is a hardware cursor */
DP_TRUE /* Off screen repositioning supported */
}
};
const DP_UINT_8 DP_aui8ColourSpaceConversionModeVals [ DP_COLOUR_SPACE_CONVERSION_MODE_NUMBER_OF_MODES ] =
{
0x00,
0x01,
0x02,
0x03
};
const DP_UINT_8 DP_aui8BytesPerPixel [ DP_PIXEL_COLOUR_FORMAT_NUMBER_OF_MODES ] =
{
1, /* DP_PIXEL_COLOUR_FORMAT_8_BIT_INDEXED */
1, /* DP_PIXEL_COLOUR_FORMAT_4_BIT_INDEXED_4_BIT_ALPHA */
2, /* DP_PIXEL_COLOUR_FORMAT_8_BIT_INDEXED_8_BIT_ALPHA */
1, /* DP_PIXEL_COLOUR_FORMAT_8_BIT_RGB_332 */
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