dp_init_marathon.h

Lido PXA270平台开发板的最新BSP,包括源代码

/*********************************************************************************
 *********************************************************************************
 **
 ** Name        : dp_init_marathon.h
 ** Title       : Main initialisation header for Display Pipeline API
 ** Author      : P. Buxton
 ** Created     : June 2002
 ** 
 ** Copyright   : 2002 by Imagination Technologies Limited. All rights reserved
 **             : No part of this software, either material or conceptual
 **             : may be copied or distributed, transmitted, transcribed,
 **             : stored in a retrieval system or translated into any
 **             : human or computer language in any form by any means,
 **             : electronic, mechanical, manual or other-wise, or
 **             : disclosed to third parties without the express written
 **             : permission of Imagination Technologies Limited, Unit 8,
 **             : HomePark Industrial Estate, King's Langley, Hertfordshire,
 **             : WD4 8LZ, U.K.
 **
 ** Description : This file contains the structures, enumerations and constant
 **               definitions used by the Display Pipeline API and which are
 **               not hardware implementation specific. Such hardware dependent
 **               header information is kept in the file 'dp_hardware.h'.
 **
 ** Platform    : Platform independent	(modify 'types.h' accordingly)
 ** $Log: dp_init_marathon.h $
 **
 **  --- Revision Logs Removed --- 
 **********************************************************************************
 *********************************************************************************/

/** Enumerations and structure definitions										**/

#if !defined (__DP_INIT_H__)
#define __DP_INIT_H__


#define	DP_NO_OF_STREAMS								3
#define	DP_USE_INTERRUPTS								0

#define DP_TOTAL_NO_OF_REGISTERS						200

#define DP_MAXIMUM_COMMAND_SEQUENCE_LENGTH				250
#define DP_SIZE_OF_DISPATCHER_BUFFER_IN_ENTRIES			(DP_TOTAL_NO_OF_REGISTERS + 2)
#define DP_SIZE_OF_DISPATCHER_BUFFER_IN_BYTES			(DP_SIZE_OF_DISPATCHER_BUFFER_IN_ENTRIES * sizeof (DP_QueuedMemoryWrite))

#define	DP_NO_REG										1		/* '1' is considered an invalid register address because all	*/
																/* registers are 32 bits wide.									*/

typedef struct DP_tag_QueuedMemoryWrite
{
	DP_UINT_32			ui32TargetAddressOffset;
	DP_UINT_32			ui32TargetValue;

} DP_QueuedMemoryWrite, * DP_pQueuedMemoryWrite;

typedef enum DP_tag_ColourSpaceConversionModes
{
	DP_COLOUR_SPACE_CONVERSION_MODE_HDTV	= 0x00,
	DP_COLOUR_SPACE_CONVERSION_MODE_SDTV,
	DP_COLOUR_SPACE_CONVERSION_MODE_LEGACY_HDTV,
	DP_COLOUR_SPACE_CONVERSION_MODE_LEGACY_SDTV,

	/* New colour space conversion modes														*/

	DP_COLOUR_SPACE_CONVERSION_MODE_NUMBER_OF_MODES		/* Enumeration end marker				*/
} DP_ColourSpaceConversionModes;


typedef enum DP_tag_PixelColourFormats
{
	DP_PIXEL_COLOUR_FORMAT_8_BIT_INDEXED = 0x0,
	DP_PIXEL_COLOUR_FORMAT_4_BIT_INDEXED_4_BIT_ALPHA,
	DP_PIXEL_COLOUR_FORMAT_8_BIT_INDEXED_8_BIT_ALPHA,
	DP_PIXEL_COLOUR_FORMAT_8_BIT_RGB_332,
	DP_PIXEL_COLOUR_FORMAT_12_BIT_RGB_444_4_BIT_ALPHA,
	DP_PIXEL_COLOUR_FORMAT_15_BIT_RGB_555_1_BIT_ALPHA,
	DP_PIXEL_COLOUR_FORMAT_24_BIT_RGB_888,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_RGB_565,
	DP_PIXEL_COLOUR_FORMAT_24_BIT_RGB_888_8_BIT_ALPHA,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_YUV_420_PLANAR,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_YUV_422_UY0VY1,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_YUV_422_VY0UY1,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_YUV_422_Y0UY1V,
	DP_PIXEL_COLOUR_FORMAT_16_BIT_YUV_422_Y0VY1U,

	/* New colour formats are added here														*/

	DP_PIXEL_COLOUR_FORMAT_NUMBER_OF_MODES				/* Enumeration end marker				*/
} DP_PixelColourFormats;



typedef enum DP_tag_AlphaBlendModes
{
	DP_ALPHA_BLEND_MODE_NO_ALPHA = 0x0,
	DP_ALPHA_BLEND_MODE_GLOBAL_ALPHA,
	DP_ALPHA_BLEND_MODE_PIXEL_ALPHA,
	DP_ALPHA_BLEND_MODE_INVERT,

	/* New alpha blend modes are added here														*/

	DP_ALPHA_BLEND_MODE_NUMBER_OF_MODES
} DP_AlphaBlendModes;


typedef struct	DP_tag_TimingSettings
{
	DP_UINT_16	ui16HBPS;
	DP_UINT_16	ui16HT;
	DP_UINT_16	ui16HAS;
	DP_UINT_16	ui16HLBS;
	DP_UINT_16	ui16HFPS;
	DP_UINT_16	ui16HRBS;
	DP_UINT_16	ui16VBPS;
	DP_UINT_16	ui16VT;
	DP_UINT_16	ui16VAS;
	DP_UINT_16	ui16VTBS;
	DP_UINT_16	ui16VFPS;
	DP_UINT_16	ui16VBBS;

} DP_TimingSettings;

typedef enum DP_tag_MemoryRefreshPeriods
{
	DP_MEMORY_REFRESH_ALWAYS						= 0x00,
	DP_MEMORY_REFRESH_H_BLANK_ONLY,
	DP_MEMORY_REFRESH_V_BLANK_ONLY,
	DP_MEMORY_REFRESH_H_AND_V_BLANK
} DP_MemoryRefreshPeriods;

typedef struct DP_tag_InitData
{

	DP_BOOL						bCRCControl;
	DP_BOOL						bVerticalSyncSlaved;
	DP_BOOL						bHorizontalSyncSlaved;
	DP_BOOL						bBlankingPolarity;
	DP_BOOL						bBlankSignalDisable;
	DP_BOOL						bVerticalSyncPolarity;
	DP_BOOL						bVerticalSyncDisable;
	DP_BOOL						bHorizontalSyncPolarity;
	DP_BOOL						bHorizontalSyncDisable;	
	DP_BOOL						bInterlaceOn;
	DP_BOOL						bFieldPolarity;

	DP_BOOL						bCompositeSyncEnable;

	DP_MemoryRefreshPeriods		eMemoryRefreshPeriod;
	DP_UINT_8					ui8MemoryBurstLength;
	DP_BOOL						bVerticalScalerUnderrunControl;

	DP_TimingSettings			sTimingSettings;

} DP_InitData, *DP_pInitData;

typedef struct	img_tag_DP_Interrupts
{
	DP_TriStateSwitch	eCursor2Underrun;
	DP_TriStateSwitch	eCursor1Underrun;
	DP_TriStateSwitch	ePlane6Underrun;
	DP_TriStateSwitch	ePlane5Underrun;
	DP_TriStateSwitch	ePlane4Underrun;
	DP_TriStateSwitch	ePlane3Underrun;
	DP_TriStateSwitch	ePlane2Underrun;
	DP_TriStateSwitch	ePlane1Underrun;
	DP_TriStateSwitch	ePlane2BufferOverrun;
	DP_TriStateSwitch	ePlane1BufferOverrun;
	DP_TriStateSwitch	eVerticalBlanking_SecondField;
	DP_TriStateSwitch	eVerticalBlanking_FirstField;
	DP_TriStateSwitch	eHorizontalBlanking_SecondField;
	DP_TriStateSwitch	eHorizontalBlanking_FirstField;

} DP_Interrupts, * DP_pInterrupts;

typedef struct DP_tag_RGBColour
{
	DP_UINT_8	ui8Red;
	DP_UINT_8	ui8Green;
	DP_UINT_8	ui8Blue;
} DP_RGBColour, *DP_pRGBColour;


typedef enum DP_tag_SlaveModeSupport
{
	DP_SLAVE_MODE_HAS_SLAVE_PLANE					= 0x00,
	DP_SLAVE_MODE_IS_SLAVE_PLANE,
	DP_SLAVE_MODE_NO_SLAVE_SUPPORT
} DP_SlaveModeSupport;

typedef enum DP_tag_YUVStreamTypes
{
	DP_YUV_Y_OR_SOLE_RGB							= 0x00,
	DP_YUV_U,
	DP_YUV_V
} DP_YUVStreamTypes;

typedef enum DP_tag_DisplayActiveSettings
{
	DP_DISPLAY_FULLY_POWERED_DOWN					= 0x00,
	DP_DISPLAY_PARTIALLY_POWERED_DOWN,
	DP_DISPLAY_ENABLED
} DP_DisplayActiveSettings;

/* The capabilities table only lists facilities which cannot be divined from the field pointer	*/
/* tables																						*/
typedef struct DP_tag_Capabilities
{
	DP_BOOL				abColourSpaceConversionModesSupported	[ DP_COLOUR_SPACE_CONVERSION_MODE_NUMBER_OF_MODES ];

	DP_BOOL				abPixelModesSupported					[ DP_PIXEL_COLOUR_FORMAT_NUMBER_OF_MODES ];

	DP_BOOL				abAlphaBlendModesSupported				[ DP_ALPHA_BLEND_MODE_NUMBER_OF_MODES ];

	DP_SlaveModeSupport	eSlaveModeSupported;
	DP_UINT_8			ui8SlaveModeQualifier;

	DP_BOOL				bIsCursor;

	DP_BOOL				bPlaneOffScreenPositioningSupported;

} DP_Capabilities, *DP_pCapabilities;

typedef enum DP_tag_ERR_MESSAGES
{
	DP_ERR_NO_ERROR_CHECKING										= 0x00,
	DP_ERR_EXCEEDS_CAPABILITIES,

	/* Any errors which are numerically less than this value should always be returned. Errors	*/
	/* greater than this value should only be returned if error reporting is enabled.			*/
	DP_CRITICAL_ERROR_END_MARKER,

	DP_ERR_NO_ERR,
	DP_ERR_OUT_OF_RANGE,
	DP_ERR_NOT_INITIALISED,
	DP_ERR_UNKNOWN_PLANE,
	DP_ERR_UNKNOWN_MODE
	

} DP_ERR_MESSAGES;

typedef enum DP_tag_DisplayTypes
{
	DP_DISPLAY_TYPE_LCD						= 0x00,
	DP_DISPLAY_TYPE_TV_PAL,
	DP_DISPLAY_TYPE_TV_NTSC,
	DP_DISPLAY_TYPE_TV_PALM,
	DP_DISPLAY_TYPE_TV_PALN

} DP_DisplayTypes;

typedef enum DP_tag_SourceDataTypes
{
	DP_SOURCE_DATA_TYPE_PROGRESSIVE			= 0x00,
	DP_SOURCE_DATA_TYPE_FIELDS,
	DP_SOURCE_DATA_TYPE_INTERLACED_FIELDS,

	DP_SOURCE_DATA_TYPE_UNKNOWN

} DP_SourceDataTypes;

typedef struct DP_tag_FieldTarget
{
	DP_UINT_8	ui8SourceBitfieldStart;	

	DP_UINT_32	ui32TargetAddressOffset;
	DP_UINT_8	ui8TargetBitfieldStart;
	DP_UINT_32	ui32TargetBitfieldMask;

} DP_FieldTarget, *DP_pFieldTarget;



typedef struct DP_tag_CSCCoeffs
{
	DP_UINT_16							pui16RyCoeff;
	DP_UINT_16							pui16RuCoeff;
	DP_UINT_16							pui16RvCoeff;
	DP_UINT_16							pui16GyCoeff;
	DP_UINT_16							pui16GuCoeff;
	DP_UINT_16							pui16GvCoeff;
	DP_UINT_16							pui16ByCoeff;
	DP_UINT_16							pui16BuCoeff;
	DP_UINT_16							pui16BvCoeff;

} DP_CSCCoeffs, *DP_pCSCCoeffs;


typedef struct	DP_tag_VESAGTFSettings
{
	DP_UINT_16	ui16HorizontalBorder1;
	DP_UINT_16	ui16HorizontalActive;
	DP_UINT_16	ui16HorizontalBorder2;
	DP_UINT_16	ui16HorizontalFrontPorch;
	DP_UINT_16	ui16HorizontalSync;
	DP_UINT_16	ui16HorizontalBackPorch;
	DP_UINT_16	ui16VerticalBorder1;
	DP_UINT_16	ui16VerticalActive;
	DP_UINT_16	ui16VerticalBorder2;
	DP_UINT_16	ui16VerticalFrontPorch;
	DP_UINT_16	ui16VerticalSync;
	DP_UINT_16	ui16VerticalBackPorch;

} DP_VESAGTFSettings;



/* Definitions of fields written to as the result of API calls									*/


typedef enum DP_tag_FieldNames
{

	/**************************/ 
	/* Stream specific fields */
	/**************************/

	/* Alpha blend related fields																*/
	DP_STREAM_SPECIFIC_FIELD_ALPHA_BLEND_MODE						= 0x00,
	DP_STREAM_SPECIFIC_FIELD_ALPHA_BLEND_MASTER_VALUE,

	/* Blinking related fields																	*/
	DP_STREAM_SPECIFIC_FIELD_BLINKING_SOURCE_ALTERNATE,			
	DP_STREAM_SPECIFIC_FIELD_BLINKING_RATE,					

	/* Colour key related fields																*/
	DP_STREAM_SPECIFIC_FIELD_COLOUR_KEY_ENABLED,				
	DP_STREAM_SPECIFIC_FIELD_COLOUR_KEY_AGAINST_THIS_PLANE,	
	DP_STREAM_SPECIFIC_FIELD_COLOUR_KEY_COLOUR,				
	DP_STREAM_SPECIFIC_FIELD_COLOUR_KEY_MASK,				

	/* Colour space conversion related fields													*/
	DP_STREAM_SPECIFIC_FIELD_COLOUR_SPACE_CONVERSION_ENABLED,
	DP_STREAM_SPECIFIC_FIELD_COLOUR_SPACE_CONVERSION_MODE,	

	/* Gamma correction related fields															*/
	DP_STREAM_SPECIFIC_FIELD_GAMMA_CORRECTION_ENABLED,		

	/* Graphics wrapping related fields															*/
	DP_STREAM_SPECIFIC_FIELD_GRAPHICS_WRAPPING_ENABLED,		

	/* Palette related fields																	*/
	DP_STREAM_SPECIFIC_FIELD_PALETTE_ENABLED,				

	/* Pixel colour format related fields														*/
	DP_STREAM_SPECIFIC_FIELD_PIXEL_COLOUR_FORMAT,
	DP_STREAM_SPECIFIC_FIELD_COSITED_LUMA_SAMPLES,

	/* Source frame and image related fields													*/
	DP_STREAM_SPECIFIC_FIELD_SOURCE_FRAME_XPOS,					
	DP_STREAM_SPECIFIC_FIELD_SOURCE_FRAME_YPOS,										
	DP_STREAM_SPECIFIC_FIELD_SOURCE_IMAGE_HEIGHT,				

	/* Slave Plane related fields																*/
	DP_STREAM_SPECIFIC_FIELD_SLAVE_PLANE_ENABLED,			

	/* Source buffer related fields																*/
	DP_STREAM_SPECIFIC_FIELD_SOURCE_BUFFER_BASE_ADDRESS,		
	DP_STREAM_SPECIFIC_FIELD_SOURCE_BUFFER_U_ADDRESS,		
	DP_STREAM_SPECIFIC_FIELD_SOURCE_BUFFER_V_ADDRESS,		
	DP_STREAM_SPECIFIC_FIELD_SOURCE_BUFFER_STRIDE,	
	DP_STREAM_SPECIFIC_FIELD_UV_STRIDE_HALVED,
	DP_STREAM_SPECIFIC_FIELD_INTERLACED,

	/* Draw order related fields																*/
	DP_STREAM_SPECIFIC_FIELD_DRAW_ORDER_POSITION,			

	/* Source and destination frame related fields												*/
	DP_STREAM_SPECIFIC_FIELD_DESTINATION_FRAME_XPOS,					
	DP_STREAM_SPECIFIC_FIELD_DESTINATION_FRAME_YPOS,					
	DP_STREAM_SPECIFIC_FIELD_SOURCE_FRAME_WIDTH,					
	DP_STREAM_SPECIFIC_FIELD_SOURCE_FRAME_HEIGHT,					
	DP_STREAM_SPECIFIC_FIELD_PLANE_VISIBLE,

	/* Video scaler related fields																*/
	DP_STREAM_SPECIFIC_FIELD_VIDEO_SCALER_HORIZONTAL_BYPASS,
	DP_STREAM_SPECIFIC_FIELD_VIDEO_SCALER_VERTICAL_BYPASS,
	DP_STREAM_SPECIFIC_FIELD_VIDEO_SCALER_SCALING_ORDER,
	DP_STREAM_SPECIFIC_FIELD_VIDEO_SCALER_VERTICAL_FILTER_ORDER,
	DP_STREAM_SPECIFIC_FIELD_VIDEO_SCALER_VERTICAL_PITCH,