mithra_reg_defs.h

Lido PXA270平台开发板的最新BSP,包括源代码

/**************************************************************************
 * Name         : mithra_reg_defs.h
 * Title        : Mithra hardware definitions main header
 * Author       : Mike Brassington
 * Created      : 1st August 2002
 *
 * Copyright    : 2002 by Imagination Technologies Ltd. All rights reserved.
 *              : No part of this software, either material or conceptual 
 *              : may be copied or distributed, transmitted, transcribed,
 *              : stored in a retrieval system or translated into any 
 *              : human or computer language in any form by any means,
 *              : electronic, mechanical, manual or other-wise, or 
 *              : disclosed to third parties without the express written
 *              : permission of Imagination Technologies Ltd, Unit 8,
                : HomePark Industrial Estate, King's Langley, Hertfordshire,
 *              : WD4 8LZ, U.K.
 *
 * Description  : Builds ROM image from bin files supplied. Amends size
 *              : and calculates the sum check
 *
 * Platform     : Embedded
 *
 * Modifications:-
 * $Log: mithra_reg_defs.h $
 *
 *  --- Revision Logs Removed --- 
 *
 *  --- Revision Logs Removed --- 
 *
 *  --- Revision Logs Removed --- 
 *
 *  --- Revision Logs Removed --- 
 *
 *  --- Revision Logs Removed --- 
 *
 **************************************************************************/

#if !defined (__MITHRA_REG_DEFS_H__)

#define __MITHRA_REG_DEFS_H__


#if !defined (_WIN32)

/* include Meta based definitions */
#include <machine.inc>
#include <metagtbi.h>

#endif

/*
 * define basic offsets based on a 32bit slot
 */
#define	B32_PDP_REGISTER_OFFSET					0x1000
#define	B32_TVE_REGISTER_OFFSET					0x1000

#define	B32_AV_REGISTER_OFFSET					0x4000
#define	B32_AV_CDIF_REGISTER_OFFSET				0x4400
#define B32_AV_PIF_REGISTER_OFFSET				0x4800

#define	B32_MPG_REGISTER_OFFSET					0x0000
#define	B32_BITBLT_REGISTER_OFFSET				0x5000
#define	B32_GPIO_REGISTER_OFFSET				0x7000
#define	B32_SC_REGISTER_OFFSET					0x6000
#define	B32_SDRAM_REGISTER_OFFSET				0x2000
#define	B32_DMAC_REGISTER_OFFSET				0xD000
#define	B32_ATAPI_REGISTER_OFFSET				0x3000
#define	B32_EXP_PORT_REGISTER_OFFSET			0x8000
#define	B32_RTC_REGISTER_OFFSET					0xE000
#define	B32_SYSTEM_CONTROL_REGISTER_OFFSET		0x2800
#define	B32_INFRARED_REGISTER_OFFSET			0xB000
#define B32_AUDIO_DAC_REGISTER_OFFSET			0x7800
#define	B32_CDS_REGISTER_OFFSET					0x9800
#define	B32_FILTER_REGISTER_OFFSET				0xA000
#define B32_CSS_ASSIST_REGISTER_OFFSET			0xE800


#if defined BUILD4_64BIT

/* define System register sizes */

#define SLOT_SIZE		3		/* 64 bit slot */

#define	PDP_REGISTER_OFFSET					(B32_PDP_REGISTER_OFFSET << 1)

#define	AV_REGISTER_OFFSET					(B32_AV_REGISTER_OFFSET << 1)
#define	AV_CDIF_REGISTER_OFFSET				(B32_AV_CDIF_REGISTER_OFFSET << 1)
#define AV_AVPIF_REGISTER_OFFSET			(B32_AV_PIF_REGISTER_OFFSET << 1)

#define	MPG_REGISTER_OFFSET					(B32_MPG_REGISTER_OFFSET << 1)
#define	TVE_REGISTER_OFFSET					(B32_TVE_REGISTER_OFFSET << 1)
#define	BITBLT_REGISTER_OFFSET				(B32_BITBLT_REGISTER_OFFSET << 1)
#define	GPIO_REGISTER_OFFSET				(B32_GPIO_REGISTER_OFFSET << 1)
#define	SC_REGISTER_OFFSET					(B32_SC_REGISTER_OFFSET << 1)
#define	SDRAM_REGISTER_OFFSET				(B32_SDRAM_REGISTER_OFFSET << 1)
#define	DMAC_REGISTER_OFFSET				(B32_DMAC_REGISTER_OFFSET << 1)
#define	ATAPI_REGISTER_OFFSET				(B32_ATAPI_REGISTER_OFFSET << 1)
#define	EXP_PORT_REGISTER_OFFSET			(B32_EXP_PORT_REGISTER_OFFSET << 1)
#define	RTC_REGISTER_OFFSET					(B32_RTC_REGISTER_OFFSET << 1)
#define	SYSTEM_CONTROL_REGISTER_OFFSET		(B32_SYSTEM_CONTROL_REGISTER_OFFSET << 1)
#define	INFRARED_REGISTER_OFFSET			(B32_INFRARED_REGISTER_OFFSET << 1)
#define AUDIO_DAC_REGISTER_OFFSET			(B32_AUDIO_DAC_REGISTER_OFFSET << 1)
#define	CDS_REGISTER_OFFSET					(B32_CDS_REGISTER_OFFSET << 1)
#define	FILTER_REGISTER_OFFSET				(B32_FILTER_REGISTER_OFFSET << 1)
#define CSS_ASSIST_REGISTER_OFFSET			(B32_CSS_ASSIST_REGISTER_OFFSET << 1)


#define START_OF_REGISTER_SPACE				(0x06000000)
#define REGISTER_SPACE_SIZE					(0x00020000)

#else

#define SLOT_SIZE		2		/* 32 bit slot */

#define	PDP_REGISTER_OFFSET					(B32_PDP_REGISTER_OFFSET)

#define	AV_REGISTER_OFFSET					(B32_AV_REGISTER_OFFSET)
#define	AV_CDIF_REGISTER_OFFSET				(B32_AV_CDIF_REGISTER_OFFSET)
#define AV_AVPIF_REGISTER_OFFSET			(B32_AV_PIF_REGISTER_OFFSET)

#define	MPG_REGISTER_OFFSET					(B32_MPG_REGISTER_OFFSET)
#define	TVE_REGISTER_OFFSET					(B32_TVE_REGISTER_OFFSET)
#define	BITBLT_REGISTER_OFFSET				(B32_BITBLT_REGISTER_OFFSET)
#define	GPIO_REGISTER_OFFSET				(B32_GPIO_REGISTER_OFFSET)
#define	SC_REGISTER_OFFSET					(B32_SC_REGISTER_OFFSET)
#define	SDRAM_REGISTER_OFFSET				(B32_SDRAM_REGISTER_OFFSET)
#define	DMAC_REGISTER_OFFSET				(B32_DMAC_REGISTER_OFFSET)
#define	ATAPI_REGISTER_OFFSET				(B32_ATAPI_REGISTER_OFFSET)
#define	EXP_PORT_REGISTER_OFFSET			(B32_EXP_PORT_REGISTER_OFFSET)
#define	RTC_REGISTER_OFFSET					(B32_RTC_REGISTER_OFFSET)
#define	SYSTEM_CONTROL_REGISTER_OFFSET		(B32_SYSTEM_CONTROL_REGISTER_OFFSET)
#define	INFRARED_REGISTER_OFFSET			(B32_INFRARED_REGISTER_OFFSET)
#define AUDIO_DAC_REGISTER_OFFSET			(B32_AUDIO_DAC_REGISTER_OFFSET)
#define	CDS_REGISTER_OFFSET					(B32_CDS_REGISTER_OFFSET)
#define	FILTER_REGISTER_OFFSET				(B32_FILTER_REGISTER_OFFSET)
#define CSS_ASSIST_REGISTER_OFFSET			(B32_CSS_ASSIST_REGISTER_OFFSET)

#define START_OF_REGISTER_SPACE				(0x04000000)
#define REGISTER_SPACE_SIZE					(0x00010000)

#endif


#define	AV_CDIF_BASE_ADDRESS_OFFSET_FROM_AV	(AV_CDIF_REGISTER_OFFSET - AV_REGISTER_OFFSET)


#endif /* __MITHRA_REG_DEFS_H__ */


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