pvr3dif.h

Lido PXA270平台开发板的最新BSP,包括源代码

/*!****************************************************************************
@File			pvr3dif.h

@Title			rendering and tile accelerator structures

@Author			Imagination Technologies

@date   		10th May 2002
 
@Copyright     	Copyright 2003-2004 by Imagination Technologies Limited.
                All rights reserved. No part of this software, either
                material or conceptual may be copied or distributed,
                transmitted, transcribed, stored in a retrieval system
                or translated into any human or computer language in any
                form by any means, electronic, mechanical, manual or
                other-wise, or disclosed to third parties without the
                express written permission of Imagination Technologies
                Limited, Unit 8, HomePark Industrial Estate,
                King's Langley, Hertfordshire, WD4 8LZ, U.K.

@Platform		cross platform / environment

@Description	rendering and tile accelerator structures

@DoxygenVer		

******************************************************************************/

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#if !defined (__PVR3DIF_H__)

#define __PVR3DIF_H__


#define	PVR3DIF_3DCTL_FREE				0	/*!< Scene Resources State, Free */
#define PVR3DIF_3DCTL_PREPARING			1	/*!< Scene Resources State, Preparing (TA'ing) */
#define PVR3DIF_3DCTL_CS_PREPARING		2	/*!< Scene Resources State, complex scene preparing */
#define PVR3DIF_3DCTL_PREPARED			3	/*!< Scene Resources State, prepared (ready to render) */

#define MBX_BACKGROUNDOBJ_UPDATE_SIZE	6	/*!< Background object state update size */

#define	PVR3DIF_3D_OVL_BLIT_BG_OBJ_SIZE			22
#define	PVR3DIF_3DBLIT_BG_OBJ_SIZE				26
#define PVR3DIF_3DBLIT_VIEWPORT_OBJ_SIZE		13
#define PVR3DIF_3DBLIT_SRCCOPY_OBJ_SIZE			44//FIXME: split this into ovl/bgo defines (44/33)
#define PVR3DIF_3DBLIT_MAX_VIEWPORT_COUNT		32


/*!
 *****************************************************************************
 * Shared data structure between 3DCtl(KM) and TARenderInfo(UM) Rendering
 * and TA interface structures
 *****************************************************************************/
typedef struct _PVR3DIF_SHAREDDATA_ {
	volatile IMG_UINT32	aui32HWContextID[2];	/*!< Double Buffered record of HWcontextID in use by a scene */
	IMG_UINT32			ui32CurrentRenderData;	/*!< Index into aui32HWContextID, asRgnHeaderDevVAddr and aui32ContextStatus */
	IMG_UINT32			ui32TilesX;				/*!< No. of tiles in X bounding the render target */
	IMG_UINT32			ui32TilesY;				/*!< No. of tiles in Y bounding the render target */
	IMG_UINT32			ui32XTilesPerMT;		/*!< No of tiles in a macros tile in X */
	IMG_UINT32			ui32YTilesPerMT;		/*!< No of tiles in a macros tile in Y */
	IMG_UINT32			ui32MTilesX;			/*!< No. of Macros tiles in X, n.b ui32MTilesX*ui32XTilesPerMT may not == ui32TilesX */
	IMG_UINT32			ui32MTilesY;			/*!< No. of Macros tiles in Y, n.b ui32MTilesY*ui32YTilesPerMT may not == ui32TilesY */
	IMG_DEV_VIRTADDR	ParamBuffDevVAddr;		/*!< Param Buffer Base Address (Device Virtual Address) */
	IMG_DEV_VIRTADDR	TAContextDevVAddr;		/*!< TA context load/store address (Device Virtual Address) */
	IMG_DEV_VIRTADDR	EVMContextDevVAddr;		/*!< EVM context load/store address (Device Virtual Address) */
	IMG_DEV_VIRTADDR	asRgnHeaderDevVAddr[2];	/*!< Double Buffered Region headers (Device Virtual Address) */
	IMG_VOID			*pvTailPtrsKM;			/*!< Tail pointers (CPU linear address) */
	IMG_DEV_VIRTADDR	TailPtrDevVAddr;		/*!< Tail pointers (Device Virtual Address)*/
	IMG_UINT32			ui32TailPtrSize;		/*!< Tail pointers size in bytes */
	volatile IMG_UINT32	aui32ContextStatus[2];	/*!< Double buffered scene status */
	volatile IMG_BOOL	bAllocateDepthbuffer;	/*!< Allocate Zbuffer hint to client 3D API */
	volatile IMG_BOOL	bSceneInvalidated;		/*!< signal to 3DAPI client to invalid scene - reset on new scene */
	IMG_UINT32			ui32UniqueID;			/*!< Unique ID used to TA context switch */
	IMG_UINT32			ui32AAFlags;			/*!< Anti aliasing flags */
	PVRSRV_HWREG		asMidSceneModRegs[2];	/*!< (D3DM) Registers to modify if we've had to do a mid scene render */	
	IMG_UINT32			ui32MidSceneModRegCount;/*!< (D3DM) Count of mid scene mod registers */
}PVR3DIF_SHAREDDATA;
	

/*!
 ****************************************************************************
 * Kernel side structure for Rendering and TA interface structures
 *****************************************************************************/
typedef struct _PVR3DIF_3DCTL_
{
	/* This shared data must be at the top of the structure */
	PVR3DIF_SHAREDDATA				sSharedData;		/*!< KM/UM Shared Data */

	PPVRSRV_CSINFO					psCSInfoKM;			/*!< Complex scene linked-list head node  */
	PPVRSRV_CSINFO					psCSInfoMemKM;		/*!< Complex scene linked-list memory  */

	IMG_VOID						*pvTAContextKM;		/*!< TA context, KM CPU linear address */
	IMG_VOID						*pvEVMContextKM;	/*!< EVM context, KM CPU linear address */
	IMG_VOID						*apvRgnHeadersKM[2];/*!< Region headers, KM CPU linear address */							

	IMG_VOID						*pvBackgroundObjectKM;	/*!< Background Object, KM CPU linear address */
	IMG_UINT32						aui32BackgroundObjUpdate[MBX_BACKGROUNDOBJ_UPDATE_SIZE];
															/*!< Background Object update Data */
	IMG_UINT32						ui32RegionHeaderSize;	/*!< Region header Size in bytes */
									
	PRESMAN_ITEM					psResItem;				/*!< Resource manager item */
									
	struct _PVR3DIF_3DCTL_			*psNext;				/*!< Pointer to next in the list */
} PVR3DIF_3DCTL;


/*!
 ****************************************************************************
 * Kernel side structure for 3D blit control
 *****************************************************************************/
typedef struct _PVR3DIF_BLITCTL_
{
	IMG_VOID						*pvRgnHeadersKM;		/*!< Region headers, KM CPU linear address */							
	IMG_DEV_VIRTADDR				sRgnHeaderDevVAddr;	/*!< Region headers (Device Virtual Address) */
	
	IMG_VOID						*pvObjDataKM;			/*!< Object data address */
	IMG_DEV_VIRTADDR				sObjDataDevVAddr;		/*!< Object data dev. virtual address */
	
	IMG_UINT32						ui32NumTilesX;			/*!< tiles in X */
	IMG_UINT32						ui32NumTilesY;			/*!< tiles in Y */
			
	volatile IMG_BOOL				abRegionsInUse;		/*!< Double buffered region header status */

	PVR3DIF_3DCTL					s3DCtl;

	IMG_UINT32						*pui32PtrBase;					 /*!< base of ptr list */
	IMG_UINT32						*apui32VPObj[PVR3DIF_3DBLIT_MAX_VIEWPORT_COUNT];/*!< list of ptrs to bases of VP obj data blocks */
	IMG_UINT32						*pui32SRCCOPYObj;				 /*!< ptr to base of SRCCOPY obj data */
	IMG_UINT32						*pui32ColourFillObj;			 /*!< ptr to base of ColourFill obj data */
	IMG_UINT32						aui32PtrListCopy[PVR3DIF_3DBLIT_MAX_VIEWPORT_COUNT+3];
	
} PVR3DIF_BLITCTL;

/*!
 ****************************************************************************
 * Kernel side structure for 3D Overlay blit control
 *****************************************************************************/
#define MAX_OVERLAY_BLIT_REGS 15
typedef struct _PVR3DIF_OVL_BLITCTL_
{
	IMG_VOID						*pvRgnHeadersKM;	/*!< Region headers, KM CPU linear address */							
	IMG_DEV_VIRTADDR				sRgnHeaderDevVAddr;	/*!< Double Buffered Region headers (Device Virtual Address) */
	
	IMG_VOID						*pvObjDataKM;		/*!< Object data address */
	IMG_DEV_VIRTADDR				sObjDataDevVAddr;	/*!< Object data dev. virtual address */
	
	IMG_UINT32						ui32NumTilesX;			/*!< tiles in X */
	IMG_UINT32						ui32NumTilesY;			/*!< tiles in Y */
			
	PVR3DIF_3DCTL					s3DCtl;

	IMG_UINT32						ui32TexFormatStride; /*!< BGO data */
	IMG_UINT32						ui32TexAddrStride;

	IMG_UINT32						ui32SrcStride;
	IMG_UINT32						ui32SrcHeight;	

	IMG_UINT32						*pui32PtrBase;					 /*!< base of ptr list */
	IMG_UINT32						*pui32RotatedSRCCOPYObj[12];	 /*!< ptr to base of rotated SRCCOPY obj's data */
	PVRSRV_HWREG					asOverlayBlitRegs[MAX_OVERLAY_BLIT_REGS];
	
} PVR3DIF_OVL_BLITCTL;

/*!
 *********************************************************************************
 *	Complex Scene MacroTile Zload list required for multiple partial renders
 *	and Zload at final render
 *********************************************************************************/
typedef struct _PVR_CS_INFO_
{
	PMBX1_REGION_ENTRY	psRegionHdr;	   /* CPU linear address to actual region headers (per macro tile) */
	IMG_DEV_VIRTADDR	RgnHeaderDevVAddr; /*!< region header device virtual address for macro tile */

#if defined (FIX_HW_PRN_264_MBX)
	IMG_UINT32 ui32MacroTileXOffsetInTiles;
	IMG_UINT32 ui32MacroTileYOffsetInTiles;
#endif

	struct _PVR_CS_INFO_ *psNext;		   /*!< pointer to next one */
} PVR_CS_INFO, *PPVR_CS_INFO;


/*!
 *********************************************************************************
 * Global parameter buffer definition structure
 ********************************************************************************/
typedef struct _PVR3DIF_PARAMBUFFER_
{
	IMG_UINT32					ui32TotalPBSize;		/*!< Size of parameter buffer in bytes */
	IMG_UINT32					ui32NumBlocks;			/*!< number of managed blocks (memory pages) */
	IMG_VOID					*pvParamLinBaseKM;		/*!< KM CPU linear address of parameter buffer */
	IMG_VOID					*pvPageTableLinBaseKM;	/*!< KM CPU linear address of page table */
	IMG_DEV_VIRTADDR			PageTableDevVAddr;		/*!< device virtual address of page table */
	IMG_DEV_VIRTADDR			ParamDevVAddr;			/*!< device virtual address of parameter buffer */
	IMG_UINT32					ui32HWRegCount;			/*!< HW register count for initialising parameter buffer */
	PVRSRV_HWREG				asHWRegs[7];			/*!< HW register values for initialising parameter buffer */
	PVR3DIF_3DCTL				*ps3DCtlList;			/*!< Linked list of RTA structures using this parameter buffer */
	IMG_VOID					*pvBGOPageShadow;		/*!< Shadow of first page of object data for power events */
} PVR3DIF_PARAMBUFFER;


#endif /* __PVR3DIF_H__ */

/*--------------------------------- end of file ------------------------------*/