sysutils.c

Lido PXA270平台开发板的最新BSP,包括源代码

/*******************************************************************************
<module>
* Name         : sysutils.c
* Title        : Shared (User/kernel) and System dependent utilities
* Author       : Dave Roberts
* Created      : 16 / 9 / 03
*
* Copyright    : 2003 by Imagination Technologies Limited.
*                All rights reserved.  No part of this software, either
*                material or conceptual may be copied or distributed,
*                transmitted, transcribed, stored in a retrieval system
*                or translated into any human or computer language in any
*                form by any means, electronic, mechanical, manual or
*                other-wise, or disclosed to third parties without the
*                express written permission of Imagination Technologies
*                Limited, Unit 8, HomePark Industrial Estate,
*                King's Langley, Hertfordshire, WD4 8LZ, U.K.
*
* Description  : This header provides system-specific functions
*
* Platform     : WinCE
*
* Modifications:-
* $Log: sysutils.c $
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</module>
********************************************************************************/
#if defined(PVR_KERNEL)
	#include "services_headers.h"
#else
	#include "img_defs.h"
	#include "services.h"
	#include "hostfunc_um.h"
	#include "pvr_debug.h"
#endif

#include "mbx1defs.h"
#include "pdpdefs.h"
#include "syscommon.h"
#include "sharedutils.h"




/*!
******************************************************************************

 @Function	SysDecodeDeviceInterrupts
 
 @Description 	decode device interrupts
 
 @Return   none

******************************************************************************/
IMG_UINT32 SysDecodeDeviceInterrupts(PVRSRV_DEV_INFO *psDevInfo, IMG_PVOID pvLinRegBaseAddr)
{
	IMG_UINT32 ui32Offset = 0;
	
	switch(psDevInfo->sDevId.eDeviceClass)
	{
		case PVRSRV_DEVICE_CLASS_3D :
		{
			ui32Offset = MBX1_GLOBREG_INT_STATUS;
			break;	
		}
		case PVRSRV_DEVICE_CLASS_DISPLAY :
		{
			ui32Offset = PDP_INTSTATUS;
			break;
		}
		case PVRSRV_DEVICE_CLASS_MPEG :
			/* TODO */

		default :
		{
			PVR_DPF((PVR_DBG_ERROR, "DecodeInterrupts: invalid device class"));
			PVR_ASSERT(0);
			return 0;
		}
	}
	
	/* just return what you read */
	return ReadHWReg(pvLinRegBaseAddr, ui32Offset);
}


/*!
******************************************************************************

 @Function	SysEnableDeviceInterrupts
 
 @Description 	enable device interrupts
 
 @Return   original state

******************************************************************************/
IMG_UINT32 SysEnableDeviceInterrupts(PVRSRV_DEV_INFO *psDevInfo,
						           IMG_PVOID pvLinRegBaseAddr,
						           IMG_UINT32 ui32Interrupts)
{
	IMG_UINT32 ui32Offset, uOrigVal;
	
	switch(psDevInfo->sDevId.eDeviceClass)
	{
		case PVRSRV_DEVICE_CLASS_3D :
		{
			ui32Offset = MBX1_GLOBREG_INT_MASK;
			break;	
		}
		case PVRSRV_DEVICE_CLASS_DISPLAY :
		{
			ui32Offset = PDP_INTENABLE;
			break;
		}
		case PVRSRV_DEVICE_CLASS_MPEG :
			/* TODO */
		default :
		{
			PVR_DPF((PVR_DBG_ERROR, "EnableInterrupts: invalid device class"));
			PVR_ASSERT(0);
			return(0);
		}
	}

	/* remember old value */
	uOrigVal = ReadHWReg(pvLinRegBaseAddr, ui32Offset);

	/* just mask out the specified value (no need to invert) */
	WriteHWReg(pvLinRegBaseAddr, ui32Offset, uOrigVal | ui32Interrupts);

	return uOrigVal;
}


/*!
******************************************************************************

 @Function	SysDisableDeviceInterrupts
 
 @Description 	disable device interrupts
 
 @Return   original state

******************************************************************************/
IMG_UINT32 SysDisableDeviceInterrupts(PVRSRV_DEV_INFO *psDevInfo,
									  IMG_PVOID pvLinRegBaseAddr,
									  IMG_UINT32 ui32Interrupts)
{
	IMG_UINT32 ui32Offset, uOrigVal;
	
	switch(psDevInfo->sDevId.eDeviceClass)
	{
		case PVRSRV_DEVICE_CLASS_3D :
		{
			ui32Offset = MBX1_GLOBREG_INT_MASK;
			break;	
		}
		case PVRSRV_DEVICE_CLASS_DISPLAY :
		{
			ui32Offset = PDP_INTENABLE;
			break;
		}
		case PVRSRV_DEVICE_CLASS_MPEG :
			/* TODO */
		default :
		{
			PVR_DPF((PVR_DBG_ERROR, "DisableInterrupts: invalid device class"));
			PVR_ASSERT(0);
			return 0;
		}
	}

	/* remember old value */
	uOrigVal = ReadHWReg(pvLinRegBaseAddr, ui32Offset);
	
	WriteHWReg(pvLinRegBaseAddr, ui32Offset, uOrigVal & ~ui32Interrupts);

	return uOrigVal;
}


/*!
******************************************************************************

 @Function	SysClearDeviceInterrupts
 
 @Description 	clear device interrupts
 
 @Return   none

******************************************************************************/
IMG_VOID SysClearDeviceInterrupts(PVRSRV_DEV_INFO *psDevInfo,
								  IMG_PVOID pvLinRegBaseAddr,
								  IMG_UINT32 ui32Interrupts)
{
	IMG_UINT32 ui32Offset;
	
	switch(psDevInfo->sDevId.eDeviceClass)
	{
		case PVRSRV_DEVICE_CLASS_3D :
		{
			ui32Offset = MBX1_GLOBREG_INT_CLEAR;
			break;	
		}
		case PVRSRV_DEVICE_CLASS_DISPLAY :
			/* n.b. this isn't wrong - we clear by writing to the status */
			ui32Offset = PDP_INTSTATUS;
			break;

		case PVRSRV_DEVICE_CLASS_MPEG :
			/* TODO */

		default :
		{
			PVR_DPF((PVR_DBG_ERROR, "ClearInterrupts: invalid device class"));
			PVR_ASSERT(0);
			return;
		}
	}

	/* just write the value directly (no need to invert) */
	WriteHWReg(pvLinRegBaseAddr, ui32Offset, ui32Interrupts);
}



/*!
******************************************************************************

 @Function  SysKickCmdProc
 
 @Description 
 
 kicks command processor
  
 @Input pvLinRegBaseAddr
 
 @Return none

******************************************************************************/
IMG_VOID SysKickCmdProc(IMG_UINT32 *pui32KickerAddr)
{
	if(pui32KickerAddr == IMG_NULL)
	{
		PVR_DPF((PVR_DBG_ERROR, "SysKickCmdProc: address"));
		return;
	}

	WriteHWReg(pui32KickerAddr, 0, SYS_KICKER_VALUE);
}


/*!
******************************************************************************

 @Function  SysCoreEnable
 
 @Description 
 
 Turn on clock of the specified core
 
 @Input psDevInfo
 
 @Input eCGCore - id of core to disable

 @Input bBlockMutex - block?
 
 @Return PVRSRV_ERROR

******************************************************************************/
PVRSRV_ERROR SysCoreEnable(PPVRSRV_DEV_INFO psDevInfo, DEV_CLOCKGATE_CORE eCGCore, IMG_BOOL bBlockMutex)
{
#ifdef MAR_NO_CLOCKCONTROL
	UNREFERENCED_PARAMETER(psDevInfo);
	UNREFERENCED_PARAMETER(eCGCore);
#else
	PVRSRV_ERROR		eError;
	PSYS_SPECIFIC_DATA	pMSysData	= psDevInfo->pvSysDataPtr;
	IMG_PVOID			pSysRegs	= psDevInfo->pvSysRegsPtr;
		
	/*
		n.b. we only protect against concurrent execution for the same device (devinfo) 
		for example both M24VA and MBX code can run this function concurrently
	*/
	eError = HostAcquireMutex (&psDevInfo->hClockGateMutex, bBlockMutex); 
	if (eError != PVRSRV_OK)
	{
		return eError;
	}

	PDUMPSCRIPT("---- SysCoreEnable start");
	PDUMPREGTAG(PDUMPTAGS_REG_MSOC, 0);

	switch (eCGCore) 
	{
		case DEV_CGCORE_MBX_2D:
			PDUMPSCRIPT("---- Enabling MBX 2D");
			if (pMSysData->bTAEnabled || pMSysData->b3DEnabled)
			{
				/* do nothing */
			}
			else if(!pMSysData->bAsync2DEnabled)
			{					
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, ((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_2D);
			}
			pMSysData->b2DEnabled = IMG_TRUE;
			break;

		case DEV_CGCORE_MBX_ASYNC_2D:
			PDUMPSCRIPT("---- Enabling MBX Async 2D");
			if (pMSysData->bTAEnabled || pMSysData->b3DEnabled)
			{
				/* do nothing */
			}
			else if(!pMSysData->b2DEnabled)
			{					
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, ((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_2D);
			}
			pMSysData->bAsync2DEnabled = IMG_TRUE;
			break;

		case DEV_CGCORE_MBX_TA:
			PDUMPSCRIPT("---- Enabling MBX 3D");
			if(!pMSysData->bTAEnabled && !pMSysData->b3DEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, ((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_ALL);
			}
			pMSysData->bTAEnabled = IMG_TRUE;
			break;

		case DEV_CGCORE_MBX_3D:
			PDUMPSCRIPT("---- Enabling MBX 3D");
			if(!pMSysData->bTAEnabled && !pMSysData->b3DEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, ((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_ALL);
			}
			pMSysData->b3DEnabled = IMG_TRUE;
			break;

		case DEV_CGCORE_M24VA:
			PDUMPSCRIPT("---- Enabling M24VA");
			WriteHWReg(pSysRegs, MAR_M24CLK_CONFIG,((pMSysData->ui32M24VADivider-1) << 1) | MAR_M24CLK_CONFIG_ON);
			break;

		case DEV_CGCORE_PDP_GRAPHICS:
			PDUMPSCRIPT("---- Enabling PDP Graphics");
			WriteHWReg(pSysRegs, MAR_PIXCLK_CONFIG, MAR_PIXCLK_CONFIG_ON);
			break;

		case DEV_CGCORE_PDP_OVERLAY:
			PDUMPSCRIPT("---- Enabling PDP Overlay");
			WriteHWReg(pSysRegs, MAR_VIDCLK_CONFIG, MAR_VIDCLK_CONFIG_ON);
			break;

		default:
			PVR_DPF((PVR_DBG_ERROR,"SysCoreEnable - *UNKNOWN*"));
			break;
	}

	PDUMPSCRIPT("---- SysCoreEnable fini");
	PDUMPREGMBX;

	eError = HostReleaseMutex (&psDevInfo->hClockGateMutex); 
	if (eError != PVRSRV_OK)
	{
		return eError;
	}
	
#endif /* #ifdef MAR_NO_CLOCKCONTROL */

	return(PVRSRV_OK);
}


/*!
******************************************************************************

 @Function  SysCoreDisable
 
 @Description 
 
 Turn off clock of the specified core
 
 @Input psDevInfo
 
 @Input eCGCore - id of core to disable

 @Input bBlockMutex - block?
 
 @Return PVRSRV_ERROR

******************************************************************************/
PVRSRV_ERROR SysCoreDisable(PPVRSRV_DEV_INFO psDevInfo, DEV_CLOCKGATE_CORE eCGCore, IMG_BOOL bBlockMutex)
{
#ifdef MAR_NO_CLOCKCONTROL
	UNREFERENCED_PARAMETER(psDevInfo);
	UNREFERENCED_PARAMETER(eCGCore);
#else
	PVRSRV_ERROR		eError;
	PSYS_SPECIFIC_DATA	pMSysData	= psDevInfo->pvSysDataPtr;
	IMG_PVOID			pSysRegs	= psDevInfo->pvSysRegsPtr;

	/* 
		n.b. we only protect against concurrent execution for the same device (devinfo) 
		for example both M24VA and MBX code can run this function concurrently
	*/
	eError = HostAcquireMutex (&psDevInfo->hClockGateMutex, bBlockMutex); 
	if (eError != PVRSRV_OK)
	{
		return eError;
	}

	PDUMPSCRIPT("---- SysCoreDisable start");
	PDUMPREGTAG(PDUMPTAGS_REG_MSOC, 0);

	switch (eCGCore) 
	{
		case DEV_CGCORE_MBX_2D:
			PDUMPSCRIPT("---- Disabling MBX 2D");
			pMSysData->b2DEnabled = IMG_FALSE;
			if (!pMSysData->bAsync2DEnabled
			&&	!pMSysData->b3DEnabled  
			&&	!pMSysData->bTAEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, MAR_MBXCLK_CONFIG_OFF);
			}
			break;

		case DEV_CGCORE_MBX_ASYNC_2D:
			PDUMPSCRIPT("---- Disabling MBX Async 2D");
			pMSysData->bAsync2DEnabled = IMG_FALSE;
			if (!pMSysData->b2DEnabled
			&&	!pMSysData->b3DEnabled  
			&&	!pMSysData->bTAEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, MAR_MBXCLK_CONFIG_OFF);
			}
			break;

		case DEV_CGCORE_MBX_TA:
			PDUMPSCRIPT("---- Disabling MBX 3D");
			pMSysData->bTAEnabled = IMG_FALSE;
			if(pMSysData->b3DEnabled)
			{
				/* do nothing */
			}
			else if(pMSysData->b2DEnabled || pMSysData->bAsync2DEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG,
							((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_2D);
			}
			else
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, MAR_MBXCLK_CONFIG_OFF);
			}
			break;

		case DEV_CGCORE_MBX_3D:
			PDUMPSCRIPT("---- Disabling MBX 3D");
			pMSysData->b3DEnabled = IMG_FALSE;
			if(pMSysData->bTAEnabled)
			{
				/* do nothing */
			}
			else if(pMSysData->b2DEnabled || pMSysData->bAsync2DEnabled)
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG,
							((pMSysData->ui32MBXDivider-1) << 2) | MAR_MBXCLK_CONFIG_2D);
			}
			else
			{
				WriteHWReg(pSysRegs, MAR_MBXCLK_CONFIG, MAR_MBXCLK_CONFIG_OFF);
			}
			break;


		case DEV_CGCORE_M24VA:
			PDUMPSCRIPT("---- Disabling M24VA");
			WriteHWReg(pSysRegs, MAR_M24CLK_CONFIG,((pMSysData->ui32M24VADivider-1) << 1) | MAR_M24CLK_CONFIG_OFF);
			break;

		case DEV_CGCORE_PDP_GRAPHICS:
			PDUMPSCRIPT("---- Disabling PDP Graphics");
			WriteHWReg(pSysRegs, MAR_PIXCLK_CONFIG, MAR_PIXCLK_CONFIG_OFF);
			break;

		case DEV_CGCORE_PDP_OVERLAY:
			PDUMPSCRIPT("---- Disabling PDP Overlay");
			WriteHWReg(pSysRegs, MAR_VIDCLK_CONFIG, MAR_VIDCLK_CONFIG_OFF);
			break;

		default:
			PVR_DPF((PVR_DBG_ERROR,"DevCoreDisable - *UNKNOWN*"));
			break;
	}

	PDUMPSCRIPT("---- SysCoreDisable fini");
	PDUMPREGMBX;

	eError = HostReleaseMutex (&psDevInfo->hClockGateMutex); 
	if (eError != PVRSRV_OK)
	{
		return eError;
	}

#endif /* #ifdef MAR_NO_CLOCKCONTROL */

	return(PVRSRV_OK);
}