📄 xlli_lowlev_init.s
字号:
str r3, [r2, #xlli_OSCR0_offset] ; Zero out count register 0
str r3, [r2, #xlli_OSCR4_offset] ; Zero out count register 4 - 11
str r3, [r2, #xlli_OSCR5_offset]
str r3, [r2, #xlli_OSCR6_offset]
str r3, [r2, #xlli_OSCR7_offset]
str r3, [r2, #xlli_OSCR8_offset]
str r3, [r2, #xlli_OSCR9_offset]
str r3, [r2, #xlli_OSCR10_offset]
str r3, [r2, #xlli_OSCR11_offset]
str r3, [r2, #xlli_OSMR0_offset] ; zero-out all 12 match registers
str r3, [r2, #xlli_OSMR1_offset]
str r3, [r2, #xlli_OSMR2_offset]
str r3, [r2, #xlli_OSMR3_offset]
str r3, [r2, #xlli_OSMR4_offset]
str r3, [r2, #xlli_OSMR5_offset]
str r3, [r2, #xlli_OSMR6_offset]
str r3, [r2, #xlli_OSMR7_offset]
str r3, [r2, #xlli_OSMR8_offset]
str r3, [r2, #xlli_OSMR9_offset]
str r3, [r2, #xlli_OSMR10_offset]
str r3, [r2, #xlli_OSMR11_offset]
ldr r1, =xlli_OSSR_ALL ; Clear the status bits - these are 'sticky' bits,
str r1, [r2, #xlli_OSSR_offset] ; These bits are cleared by writing 1's to them
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; **********************************************************************
; ********** **********
; ********** ENABLE I-CACHE, D-CACHE AND BRANCH TARGET BUFFER **********
; ********** **********
; **********************************************************************
;
; This code segment enables the Instruction Cache, Data Cache, and the Branch Target Buffer.
;
xlli_icache_enable FUNCTION
mrc p15, 0, r2, c1, c0, 0 ; Get the contents of the ARM control register
mov r2, r2, LSL #18 ; Upper 18-bits must be written as zero...
mov r2, r2, LSR #18 ; ....clear them now
orr r2, r2, #xlli_control_icache ; set the i-cache bit
orr r2, r2, #xlli_control_btb ; set the btb bit
orr r2, r2, #xlli_control_dcache ; set the d-cache bit
; This code segment writes the contents of r2 into the ARM control register.
; Note: you must either format the contents of w1 so that reserved bits
; are written with the proper value, or get the getARMControl values and
; modify the control bits you need.
;
; make sure this is first instruction in a cache line
b xlli_7
ALIGN 32
xlli_7
mcr p15, 0, r2, c1, c0, 0
; This code segment guarantees that previous writes to coprocessor 15 have
; completed. Depending on what is being modified in cp15 (turning on
; the mmu, for example), these instructions may need to be executed
; from the icache.
mrc p15, 0, r2, c1, c0, 0
mov r2, r2
sub pc, pc, #4
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; **************************************************
; ********** **********
; ********** INITIALIZE the POWER MANAGER **********
; ********** **********
; **************************************************
;
; This code initializes the Power Manager
;
xlli_pwrmgr_init FUNCTION
ldr r2, =xlli_PMRCREGS_PHYSICAL_BASE ; get base address of power mgr / reset control regs
mov r1, #0 ; clear a work register
str r1, [r2, #xlli_PWER_offset] ; Reset Power Manager Wake-up register
str r1, [r2, #xlli_PRER_offset] ; Clear Power Manager Rising-Edge Detector Enables
str r1, [r2, #xlli_PFER_offset] ; Clear Power Manager Falling-Edge Detector Enables
str r1, [r2, #xlli_PEDR_offset] ; Clear Power Manager GPIO edge-Detect Status register
str r1, [r2, #xlli_PGSR0_offset] ; Clear GPIO sleep state registers (GPIOs 31:0)
str r1, [r2, #xlli_PGSR1_offset] ; Clear GPIO sleep state registers (GPIOs 63:32)
str r1, [r2, #xlli_PGSR2_offset] ; Clear GPIO sleep state registers (GPIOs 95:64)
str r1, [r2, #xlli_PGSR3_offset] ; Clear GPIO sleep state registers (GPIOs 118:96)
str r1, [r2, #xlli_PSTR_offset] ; Reset Standby Configuration Register
str r1, [r2, #xlli_PVCR_offset] ; Reset Power Manager Voltage Change Control Register
str r1, [r2, #xlli_PKWR_offset] ; Clear Keyboard Wake-up Enable Register
str r1, [r2, #xlli_PKSR_offset] ; Clear Keyboard Edge Detect Status Register
;
; Initialize the PCFR (Power Manager General Congiguration Manager)
;
mov r1, #xlli_PCFR_OPDE ; enable 3.68Mhz power-down
; orr r1, r1, #xlli_PCFR_FP ; enable PCMCIA pin float
; orr r1, r1, #xlli_PCFR_FS ; enable static memory pin float
orr r1, r1, #xlli_PCFR_SYSEN_EN ; System power supply enable pin
str r1, [r2, #xlli_PCFR_offset]
mov r1, #1
str r1, [r2, #xlli_PWER_offset] ; Set GPIO0 wake up enable
str r1, [r2, #xlli_PFER_offset] ; Set GPIO0 Falling egde detect
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; *****************************************
; ********** **********
; ********** SET PAGE TABLE BASE **********
; ********** **********
; *****************************************
;
; Set page table base (used after a sleep reset)
;
xlli_setPTB FUNCTION
ldr r1, =xlli_p_PageTable ; Get address of Page Table base
mcr p15, 0, r1, c2, c0, 0 ; Load Page Table base into CP 15
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ***************************************************************
; ********** **********
; ********** INITIALIZE PAGE TABLES FOR MEMORY MAPPING **********
; ********** **********
; ***************************************************************
;
; Init the Page Table area of memory by writting zeros out to the table
;
xlli_initPageTable FUNCTION
ldr r1, =xlli_p_PageTable ; Get address of Page Table base
mcr p15, 0, r1, c2, c0, 0 ; Load Page Table base into CP 15
;
; zero-out the page table memory region
;
mov r2, #xlli_s_PageTable ; get table size
mov r3, #0
xlli_8
subs r2, r2, #4 ; Increment offset into table
str r3, [r1, r2] ; Clear table entry
bne xlli_8 ; Keep looping until done
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ***********************************************************
; ********** **********
; ********** INITIALIZE THE MEMORY MANAGEMENT UNIT **********
; ********** **********
; ***********************************************************
;
; Initialize the memory management unit
;
xlli_MMU_init FUNCTION
; set DACR
ldr r1, =xlli_DACR
mcr p15, 0, r1, c3, c0, 0 ; Set DACR
ldr r2, =xlli_PID
mov r2, r2, LSR #25 ; Clear the lo-order 25 bits
mov r2, r2, LSL #25 ; (may be unnecessary)
mcr p15, 0, r2, c13, c0, 0 ; Set PID
mrc p15, 0, r1, c1, c0, 1 ; Get the current aux control settings
; extract the control bits such that reserved bits are 0, this will
; prep the bits for a subsequent write.
and r1, r1, #0x33
orr r1, r1, #xlli_CONTROL_MINIDATA_01 ; orr in the mini-data cache attributes
mcr p15, 0, r1, c1, c0, 1 ; Write back the new settings
; invalidate and enable the BTB
mcr p15, 0, r1, c7, c5, 6 ; invalidate the Branch Target Buffer
;
; enable the BTB
;
mrc p15, 0, r1, c1, c0, 0
mov r1, r1, LSL #18 ; Upper 18 bits must be
mov r1, r1, LSR #18 ; written as zeros
orr r1, r1, #xlli_CONTROL_BTB ; set the BTB bit
b xlli_9 ; 1st instruction on cache line
ALIGN 32
xlli_9
mcr p15, 0, r1, c1, c0, 0 ; write the data back
mrc p15, 0, r1, c2, c0, 0 ; Insure that the write completes
mov r1, r1 ; before continuing
sub pc, pc, #4
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; **************************************************************
; ********** **********
; ********** FIRE UP THE MMU - SWITCH TO VIRTUAL MODE **********
; ********** **********
; **************************************************************
;
; Make the transistion from physical mode to virtual mode.
;
; This subroutine assumes thaqt execution is from boot ROM and that
; the MMU is disabled when this subroutine is called.
;
; NOTES:
;
; 1. The memory system must already be up and running.
; 2. The page table must be initalized (zeroed out)
; 3. The memory to be accessed must have their page table entries filled in.
; 4. The MMU needs to be initialized first.
; 5. When this subroutine returns to the caller, all addresses are virtual.
;
; Typically this would be the last low level init subroutine to be run before
; control is turned over to an operating system.
;
xlli_goVirtual FUNCTION
;
; (1) Temporarily overwrite page table entry that maps where we are now.
;
; This code section effectivly makes the table entry where the program counter
; (pc) would point now and, the table entry where the new pc value will point,
; (after going to virtual addressing) result in the code pointing to the same
; physical address regardless of which pc value is used. This is to
; cover those cases where the pc is altered after the jump to virtual
; addresing. If the sections are idenity (flat) mapped, then the following
; code basicly rewrites a single table entery with a copy of itself. Once the
; pc has been altered to the virtual address, the original table entry for the
; address space we are now is is restored to its original value.
;
; CAUTION: If the page table is mapped to virtual address different from the physical
; address, this code is likely to result in an exception to 0x10 (Data Abort) unless
; you modify the code in the section to take this into account.
;
ldr r1, =xlli_p_PageTable ; Get address of Page Table base
mov r4, pc, LSR #(20) ; Current execution location (divide by 1 Mb)
mov r4, r4, LSL #(2) ; Insure lower two bits are zero
add r4, r4, r1 ; Point to RAM page table entry for this address space
ldr r3, [r4] ; Save the existing table entry in r3
;
; Do not alter r3 or r4 as we will need them later...
;
ldr r2, =(xlli_v_xbBOOTROM :SHR: (18))
add r2, r2, r1 ; Point to new (virtual) ROM page table entry
ldr r1, [r2] ; Get this (virtural address) table entry....
;
; Overwrite RAM entry for current (physical address) table entry
;
str r1, [r4] ; ....and place it in the current table entry.
; end-of-part (1)
;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -