xlli_lowlev_init.s

Lido PXA270平台开发板的最新BSP,包括源代码

;
; INTEL CONFIDENTIAL
; Copyright 2002-2003 Intel Corporation All Rights Reserved.
;
; The source code contained or described herein and all documents
; related to the source code (Material) are owned by Intel Corporation
; or its suppliers or licensors.  Title to the Material remains with
; Intel Corporation or its suppliers and licensors. The Material contains
; trade secrets and proprietary and confidential information of Intel
; or its suppliers and licensors. The Material is protected by worldwide
; copyright and trade secret laws and treaty provisions. No part of the
; Material may be used, copied, reproduced, modified, published, uploaded,
; posted, transmitted, distributed, or disclosed in any way without Intel's
; prior express written permission.
;
; No license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise. Any license under such intellectual property rights
; must be express and approved by Intel in writing.
;
;
;*********************************************************************************
;
;  FILENAME:       xlli_LowLev_Init.s
;
;  PURPOSE:        Provides low Level init procedures written specifically for
;                  the Bulverde/XSBASE270_G platform.
;
;
;  LAST MODIFIED:  13-Oct-2003
;******************************************************************************
;
; The functions in this source code are called via a branch with link instruction.
; Unless otherwise specified, no system stack is assumed and no registers are preserved.
;
; NOTES:
;
; The use of these subroutines and/or the order in which they are called is, for the most part,
; arbitrary and is left up to the user. Only a few subroutines must be called in a specific order.
; For example, it makes no sense to go to virtual mode before the MMU is initialized and
; the page table is set up.... and, in order to set up the page table, memory needs to be initialized
; first.
;
        INCLUDE  xlli_Bulverde_defs.inc             ; Bulverde specific include file
        INCLUDE  xlli_XSBASE270_G_defs.inc                 ; XSBASE270_G specific include file
;
        AREA    |text|, CODE, READONLY, ALIGN=5         ; Align =5 required for "ALIGN 32" feature to work.
;
; List of Low Level Init functions in this source code include:
;
        EXPORT xlli_GPIO_init             ; Get SCR and LCDCR data and Initialize the GPIO ports
        EXPORT xlli_mem_init              ; Memory controller initialization
        EXPORT xlli_mem_restart           ; Restart memory controller
        EXPORT xlli_mem_Tmax              ; Sets maximum memory configuration values
        EXPORT xlli_mem_Topt              ; Sets optimal memory configuration values based on MemClk frequency
        EXPORT xlli_intr_init             ; Interrupt initialization (masks all interrupts)
        EXPORT xlli_freq_change           ; Frequency change sequence
        EXPORT xlli_clks_init             ; Initialize system clocks
        EXPORT xlli_clks_init_sleepReset  ; Initialize system clock after a sleep reset
        EXPORT xlli_ost_init              ; Initalize Operating System Timers
        EXPORT xlli_icache_enable         ; Enable I-Cache, D-Cache, and Branch Target Buffer
        EXPORT xlli_pwrmgr_init           ; Initialize the Power Manager
        EXPORT xlli_setPTB                ; Set the Page Tabe Base address (used for sleep resets)
        EXPORT xlli_initPageTable         ; Initialize Page Table for MMU unit
        EXPORT xlli_MMU_init              ; Initialize the Memory Management Unit
        EXPORT xlli_goVirtual             ; Make the transition from physical address to virtual address
        EXPORT xlli_IMpwr_init            ; Initialize Internal Memory for use
        EXPORT xlli_setClocks             ; Reads platform switchs and sets Bulverde frequencies
        EXPORT xlli_getFreq               ; Returns current system clock settings to 'C' program caller
        EXPORT xlli_setBufImpedance       ; Sets SCRAM buffer impedance (C callable)
        EXPORT xlli_setBufImp             ; Sets SCRAM buffer impedance (ROM callable)
        EXPORT xlli_switch_on             ; Check the status of power switch
        EXPORT xlli_power_off             ; Power Off (Enter Deep Sleep)

;******************************************************************************
;
;
;       ******************
;       *                *
;       * xlli_GPIO_init * Subroutine
;       *                *
;       ******************
;
; This subroutine sets up the GPIO pins in accordance with the values contained in the platform include file.
;
; NOTES: Written for the Bulverde Processor on the XSBASE270_G Development Platform.
;

xlli_GPIO_init   FUNCTION
;
;
;
;
;       Get GPIO registers base address and configure all GPIO lines.
;
        ldr     r0,  =xlli_GPIOREGS_PHYSICAL_BASE   ; Load the GPIO register block base address

        ldr     r1,  =xlli_GPSR0_value              ; Get the pin set values for GPSR0
        str     r1,  [r0, #xlli_GPSR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPSR1_value              ; Get the pin set values for GPSR1
        str     r2,  [r0, #xlli_GPSR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPSR2_value              ; Get the pin set values for GPSR2
        str     r1,  [r0, #xlli_GPSR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPSR3_value              ; Get the pin set values for GPSR3
        str     r2,  [r0, #xlli_GPSR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GPCR0_value              ; Get the pin clear values for GPCR0
        str     r1,  [r0, #xlli_GPCR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPCR1_value              ; Get the pin clear values for GPCR1
        str     r2,  [r0, #xlli_GPCR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPCR2_value              ; Get the pin clear values for GPCR2
        str     r1,  [r0, #xlli_GPCR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPCR3_value              ; Get the pin clear values for GPCR3
        str     r2,  [r0, #xlli_GPCR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GPDR0_value              ; Get the pin direction values for GPDR0
        str     r1,  [r0, #xlli_GPDR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPDR1_value              ; Get the pin direction values for GPDR1
        str     r2,  [r0, #xlli_GPDR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPDR2_value              ; Get the pin direction values for GPDR2
        str     r1,  [r0, #xlli_GPDR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPDR3_value              ; Get the pin direction values for GPDR3
        str     r2,  [r0, #xlli_GPDR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GAFR0_L_value            ; Get the pin alt function values for GAFR0_L
        str     r1,  [r0, #xlli_GAFR0_L_offset]     ; Write the R0_L values

        ldr     r2,  =xlli_GAFR0_U_value            ; Get the pin alt function values for GAFR0_U
        str     r2,  [r0, #xlli_GAFR0_U_offset]     ; Write the R0_U values

        ldr     r1,  =xlli_GAFR1_L_value            ; Get the pin alt function values for GAFR1_L
        str     r1,  [r0, #xlli_GAFR1_L_offset]     ; Write the R1_L values

        ldr     r2,  =xlli_GAFR1_U_value            ; Get the pin alt function values for GAFR1_U
        str     r2,  [r0, #xlli_GAFR1_U_offset]     ; Write the R1_U values

        ldr     r1,  =xlli_GAFR2_L_value            ; Get the pin alt function values for GAFR2_L
        str     r1,  [r0, #xlli_GAFR2_L_offset]     ; Write the R2_L values

        ldr     r2,  =xlli_GAFR2_U_value            ; Get the pin alt function values for GAFR2_U
        str     r2,  [r0, #xlli_GAFR2_U_offset]     ; Write the R2_U values

        ldr     r1,  =xlli_GAFR3_L_value            ; Get the pin alt function values for GAFR3_L
        str     r1,  [r0, #xlli_GAFR3_L_offset]     ; Write the R3_L values

        ldr     r2,  =xlli_GAFR3_U_value            ; Get the pin alt function values for GAFR3_U
        str     r2,  [r0, #xlli_GAFR3_U_offset]     ; Write the R3_U values
;
;       The RDH and PH bits on Bulverde must be set to enable updated GPIO pins.
;       These are sticky bits.
;
        ldr     r0, =xlli_PMRCREGS_PHYSICAL_BASE
        mov     r2, #(xlli_PSSR_PH | xlli_PSSR_RDH) ; Set the PH and RDH bits to enable all GPIOs
        str     r2, [r0, #xlli_PSSR_offset]         ; Enable all GPIO lines

        mov     pc, lr                              ; Return to calling program

        ENDFUNC

        LTORG

;**************************************************************************************************
;
; **************************************************
; **********                              **********
; ********** INITIALIZE MEMORY CONTROLLER **********
; **********                              **********
; **************************************************
;
; The sequence below is based on the recommended memory initializing steps detailed
; in the Bulverde EAS, Volume I (Section 13.17, page 13-72)
;

xlli_mem_init   FUNCTION

;
; ***** STEP 1: *****
;
; Delay 200 uS
;
        ldr     r2,  =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
        ldr     r3,  [r2, #xlli_OSCR0_offset]    ; Fetch starting value of OSCR0
        add     r3,  r3,  #0x300                 ; Really 0x2E1 is about 200usec, so 0x300 should be plenty
xlli_3  ldr     r1,  [r2, #xlli_OSCR0_offset]    ; Fetch current OSCR0 value
        cmp     r1,  r3                          ; Is the timer past the time out value?
        bmi     xlli_3                           ; No - Loop until it is
;
;  STEP 1 - 1st bullet: Write MSC0, MSC1 and MSC2 (the order is not important)
;  *******************
;
;       Finally - Write the memory control registers
;
        ldr     r4,  =xlli_MEMORY_CONFIG_BASE   ; Get memory controller base address

        ldr     r1,  =xlli_MSC0_value           ; Get MSC0 setting for XSBASE270_G Flash
        str     r1,  [r4, #xlli_MSC0_offset]    ; Write the value out
        ldr     r1,  [r4, #xlli_MSC0_offset]    ; Read back to latch the data

        ldr     r2,  =xlli_MSC1_value           ; Get MSC1 setting
        str     r2,  [r4, #xlli_MSC1_offset]    ; Write the value out
        ldr     r2,  [r4, #xlli_MSC1_offset]    ; Read back to latch the data

        ldr     r1,  =xlli_MSC2_value           ; Get MSC2 setting
        str     r1,  [r4, #xlli_MSC2_offset]    ; Write the value out
        ldr     r1,  [r4, #xlli_MSC2_offset]    ; Read back to latch the data
;
;  STEP 1 - 2nd bullet: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (order not important)
;  *******************
;
        ldr     r2,  =xlli_MECR_value           ; write MECR
        str     r2,  [r4, #xlli_MECR_offset]

        ldr     r1,  =xlli_MCMEM0_value         ; write MCMEM0
        str     r1,  [r4, #xlli_MCMEM0_offset]

        ldr     r2,  =xlli_MCMEM1_value         ; write MCMEM1
        str     r2,  [r4, #xlli_MCMEM1_offset]

        ldr     r1,  =xlli_MCATT0_value         ; write MCATT0
        str     r1,  [r4, #xlli_MCATT0_offset]

        ldr     r2,  =xlli_MCATT1_value         ; write MCATT1
        str     r2,  [r4, #xlli_MCATT1_offset]

        ldr     r1,  =xlli_MCIO0_value          ; write MCIO0
        str     r1,  [r4, #xlli_MCIO0_offset]

        ldr     r2,  =xlli_MCIO1_value          ; write MCIO1
        str     r2,  [r4, #xlli_MCIO1_offset]
;
;  STEP 1 - 3rd bullet: Write FLYCNFG
;  *******************
;
        ldr     r1,  =xlli_FLYCNFG_value        ; write FLYCNFG
        str     r1,  [r4, #xlli_FLYCNFG_offset]
;

;
;  STEP 1 - 4th bullet: SKIPPED (used only when coming out of sleep)
;  *******************
;
;     (If required, this would be a write to MDCNFG with enable bits deasserted.)

;
;  STEP 1 - 5th bullet: update MDREFR settings
;  *******************
;
        ldr         r2,  [r4, #xlli_MDREFR_offset] ; Get reset state of MDREFR
        mov         r2,  r2, lsr #0xC              ; Shift data 12 bits (0xC) to the right
        mov         r2,  r2, lsl #0xC              ; and shift left 12 bits (Clears DRI field)
                                                   ; because left shifts fill bits with zeros.

        ldr     r1,  =xlli_MDREFR_value            ; Fetch MDREFR value for this platform
        mov         r1,  r1, lsl #0x14             ; use shifts to extract the DRI field using
        mov         r1,  r1, lsr #0x14             ; same method as before but shifting 20 (0x14)
                                                   ; bits left, then right again.

        orr     r2,  r2, r1                    ; insert the DRI field extracted above
        str     r2,  [r4, #xlli_MDREFR_offset] ; write value with valid DRI to MDREFR

        orr     r2,  r2, #xlli_MDREFR_K0RUN    ; Enable K0RUN

        bic     r2,  r2, #xlli_MDREFR_K0DB2    ; Configure K0DB2

        orr     r2,  r2, #xlli_MDREFR_K0DB4    ; Set K0DB4 = MemClk/4

        bic     r2,  r2, #(xlli_MDREFR_K1FREE :OR: xlli_MDREFR_K2FREE)  ; Clear free run clock bits

        orr     r2,  r2, #xlli_MDREFR_K0FREE   ; Set K0FREE

        str     r2,  [r4, #xlli_MDREFR_offset] ; Write back MDREFR

        ;
        ; Preserve MDREFR in r2
        ;

; ***** STEP 2 *****
;