📄 xllp_lcd.c
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case BPP_19:
BPP = 7;
break;
case BPP_19_PACKED:
BPP = 8;
break;
case BPP_24:
BPP = 9;
break;
case BPP_25:
BPP = 10;
break;
default:
{
BPP = 0;
break;
}
}
switch(pXllpLCD->DisplayType)
{
case LTM04C380K: // 640x480 16bpp active matrix
{
//
// The actual equation requires that we take the ceiling of a floating point result.
// Rather than use floats, we'll calculate an approximation to the correct PCD value
// using integers.
//
PCD = (LCLK / (2 * LTM04C380K_PIXEL_CLOCK_FREQUENCY));
//PCD = 3; //Modify by Terry for freq
// Configure the LCD Controller Control Registers
p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM |
LCD_PAS | LCD_QDM | LCD_BM | LCD_OUM |
LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);
p_LCDRegs->LCCR1 = (LCD_PPL(0x27FU) | LCD_HSW(0x01) |
LCD_ELW(0x01) | LCD_BLW(0x8dU) ); //Modufy by Terry@2005-2-5 LCD_BLW(0x9fU)
p_LCDRegs->LCCR2 = (LCD_LPP(0x1df) | LCD_VSW(0x0) | //Modufy by Terry@2005-2-23 LCD_VFW(0x02)
LCD_EFW(0x00) | LCD_BFW(0x22) ); //Modufy by Terry@2005-2-23 LCD_BFW(0x00)
p_LCDRegs->LCCR3 = (LCD_PCD(PCD) | LCD_BPP(BPP) | LCD_PCP |
LCD_PDFOR(pXllpLCD->PixelDataFormat));
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
{
p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
}
}
break;
case LTM035A776C: // 240x320 16bpp active matrix
{
//
// The actual equation requires that we take the ceiling of a floating point result.
// Rather than use floats, we'll calculate an approximation to the correct PCD value
// using integers.
//
PCD = (LCLK / (2 * LTM035A776C_PIXEL_CLOCK_FREQUENCY));
// Configure the LCD Controller Control Registers
p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM |
LCD_PAS | LCD_QDM | LCD_BM | LCD_OUM |
LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);
p_LCDRegs->LCCR1 = (LCD_PPL(0xEF) | LCD_HSW(0x04) |
LCD_ELW(0x04) | LCD_BLW(0x05) );
p_LCDRegs->LCCR2 = (LCD_LPP(0x13f) | LCD_VSW(0x02) |
LCD_EFW(0x03) | LCD_BFW(0x02) );
p_LCDRegs->LCCR3 = (LCD_PCD(PCD) | LCD_BPP(BPP) | LCD_PCP | LCD_HSP |
LCD_PDFOR(pXllpLCD->PixelDataFormat));
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
{
p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
}
}
break;
case LM8V31: // 640x480 16bpp dual panel passive
{
//
// The actual equation requires that we take the ceiling of a floating point result.
// Rather than use floats, we'll calculate an approximation to the correct PCD value
// using integers.
//
PCD = (LCLK / (2 * LM8V31_PIXEL_CLOCK_FREQUENCY));
// Reconfigure the upper panel frame descriptors for dual panel operation by
// setting the DMA transfer length to half the size of the frame buffer
pXllpLCD->frameDescriptorCh0fd1->LDCMD = pXllpLCD->FrameBufferSize >> 1;
pXllpLCD->frameDescriptorCh0fd2->LDCMD = pXllpLCD->FrameBufferSize >> 1;
// Configure the lower panel frame descriptor for dual panel operation.
// Set the physical address of the frame descriptor
pXllpLCD->frameDescriptorCh1->FDADR = LCD_FDADR(pXllpLCD->_DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL);
// Set the physical address of the frame buffer
pXllpLCD->frameDescriptorCh1->FSADR = LCD_FSADR(pXllpLCD->_FRAME_BUFFER_BASE_PHYSICAL + pXllpLCD->CurrentPage*pXllpLCD->FrameBufferSize + (pXllpLCD->FrameBufferSize >> 1));
// Clear the frame ID
pXllpLCD->frameDescriptorCh1->FIDR = LCD_FIDR(0);
// Set the DMA transfer length to half the size of the frame buffer
pXllpLCD->frameDescriptorCh1->LDCMD = LCD_Len(pXllpLCD->FrameBufferSize >> 1);
// Store the physical address of this frame descriptor in the frame descriptor
pXllpLCD->frameDescriptorCh1->PHYSADDR = pXllpLCD->frameDescriptorCh1->FDADR;
// FBR1 is cleared and is not used in this implementation
p_LCDRegs->FBR1 = 0;
// Load the contents of FDADR1 with the physical address of this frame descriptor
p_LCDRegs->FDADR1 = pXllpLCD->frameDescriptorCh1->FDADR;
// Configure the TMED dithering engine
// Use the magic number described in the EAS, 0x00AA5500;
p_LCDRegs->TRGBR = LCD_TRS(0x00) | LCD_TGS(0x55) | LCD_TBS(0xAA);
// Use the magic number described in the EAS, 0x0000754F;
p_LCDRegs->TCR = LCD_TM2S | LCD_TM1S | LCD_TM2En | LCD_TM1En |
LCD_TVBS(0x04) | LCD_THBS(0x05) | LCD_TSCS(0x03) |
LCD_TED;
p_LCDRegs->LCCR0 = (LCD_SDS | LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PDD(0x01) | LCD_BM |
LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);
p_LCDRegs->LCCR1 = (LCD_PPL(0x27F) | LCD_HSW(0x02) |
LCD_ELW(0x03) | LCD_BLW(0x03) );
p_LCDRegs->LCCR2 = (LCD_LPP(0xef) | LCD_VSW(0x01) |
LCD_EFW(0x00) | LCD_BFW(0x00) );
p_LCDRegs->LCCR3 = (LCD_PCD(PCD) | LCD_ACB(0xff) |
LCD_PCP | LCD_BPP(BPP) |
LCD_PDFOR(pXllpLCD->PixelDataFormat));
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
{
p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
}
}
break;
case LQ64D341: // 176x220 active matrix Stinger display
{
//
// The actual equation requires that we take the ceiling of a floating point result.
// Rather than use floats, we'll calculate an approximation to the correct PCD value
// using integers.
//
PCD = (LCLK / (2 * LQ64D341_PIXEL_CLOCK_FREQUENCY));
p_LCDRegs->LCCR0 = ( LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PAS | LCD_BM |
LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);
p_LCDRegs->LCCR1 = ( LCD_PPL(0xAF) | LCD_HSW(0x02) |
LCD_ELW(0x7B) | LCD_BLW(0x03) );
p_LCDRegs->LCCR2 = ( LCD_LPP(0xdb) | LCD_VSW(0x01) |
LCD_EFW(0x02) | LCD_BFW(0x00) );
p_LCDRegs->LCCR3 = ( LCD_PCD(PCD) | LCD_BPP(BPP) |
LCD_VSP | LCD_HSP | LCD_PCP |
LCD_OEP | LCD_PDFOR(pXllpLCD->PixelDataFormat));
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
{
p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
}
}
break;
case LS022Q8DD06: // Sharp LS022Q8DD06 Sharp 240 x 320 for ZOAR
{
//
// The actual equation requires that we take the ceiling of a floating point result.
// Rather than use floats, we'll calculate an approximation to the correct PCD value
// using integers.
//
PCD = (LCLK / (2 * LS022Q8DD06_PIXEL_CLOCK_FREQUENCY));
// Configure the LCD Controller Control Registers
p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM |
LCD_PAS | LCD_QDM | LCD_BM | LCD_OUM |
LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);
p_LCDRegs->LCCR1 = (LCD_PPL(0xEF) | LCD_HSW(0x01) |
LCD_ELW(0x00) | LCD_BLW(0x07) );
p_LCDRegs->LCCR2 = (LCD_LPP(0x13f) | LCD_VSW(0x02) |
LCD_EFW(0x02) | LCD_BFW(0x00) );
p_LCDRegs->LCCR3 = (LCD_PCD(PCD) | LCD_BPP(BPP) | LCD_PCP |
LCD_PDFOR(pXllpLCD->PixelDataFormat));
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
{
p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
}
LockID = XllpLock(CKEN);
p_CLKRegs->cken = (p_CLKRegs->cken & XLLP_CLKEN_MASK) | CLK_SSP3;
XllpUnlock(LockID);
// Assert chip select on the LCD
LockID = XllpLock(GPCR2);
LockID2 = XllpLock(GPSR2);
p_GPIORegs->GPCR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPSR2 |= XLLP_GPIO_BIT_L_BIAS;
XllpOstDelayMilliSeconds(p_OSTRegs, 1);
p_SSPRegs->sscr0 = 0x00C01030;
p_SSPRegs->sscr1 = 0x00008000;
p_SSPRegs->sspsp = 0x0025000C;
p_SSPRegs->sscr0 |= 0x8F;
// Wait for the operation to complete
while(p_SSPRegs->sssr & 0x10);
for (i = 0; i < sizeof(LS022Q8DD06_DATA_SET_1) >> 1; i+=2)
{
p_GPIORegs->GPCR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPSR2 |= XLLP_GPIO_BIT_L_BIAS;
p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_1[i];
p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_1[i+1];
// Wait for the operation to complete
while(p_SSPRegs->sssr & 0x10);
XllpOstDelayMicroSeconds(p_OSTRegs, 50);
p_GPIORegs->GPSR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPCR2 |= XLLP_GPIO_BIT_L_BIAS;
XllpOstDelayMilliSeconds(p_OSTRegs, 100);
}
for (i = 0; i < sizeof(LS022Q8DD06_DATA_SET_2) >> 1; i+=2)
{
p_GPIORegs->GPCR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPSR2 |= XLLP_GPIO_BIT_L_BIAS;
p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_2[i];
p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_2[i+1];
// Wait for the operation to complete
while(p_SSPRegs->sssr & 0x10);
XllpOstDelayMicroSeconds(p_OSTRegs, 50);
p_GPIORegs->GPSR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPCR2 |= XLLP_GPIO_BIT_L_BIAS;
XllpOstDelayMilliSeconds(p_OSTRegs, 100);
}
// De-assert chip select on the LCD
p_GPIORegs->GPSR2 &= ~XLLP_GPIO_BIT_L_BIAS;
p_GPIORegs->GPCR2 |= XLLP_GPIO_BIT_L_BIAS;
XllpUnlock(LockID);
XllpUnlock(LockID2);
}
break;
default:
{
}
break;
}
}
void LCDClearStatusReg(P_XLLP_LCD_T pXllpLCD)
{
volatile LCDRegs *p_LCDRegs;
p_LCDRegs = (LCDRegs *) pXllpLCD->LCDC;
// Clear the status registers by writing 1's to each bit.
p_LCDRegs->LCSR0 = ( LCD_LDD | LCD_SOF0| LCD_BER | LCD_ABC | LCD_IU0 |
LCD_IU1 | LCD_OU | LCD_QD | LCD_EOF0| LCD_BS0 |
LCD_SINT| LCD_RD_ST | LCD_CMD_INTR );
p_LCDRegs->LCSR1 = ( LCD_SOF1| LCD_SOF2| LCD_SOF3| LCD_SOF4| LCD_SOF5 | LCD_SOF6 |
LCD_EOF1| LCD_EOF2| LCD_EOF3| LCD_EOF4| LCD_EOF5 | LCD_EOF6 |
LCD_BS1 | LCD_BS2 | LCD_BS3 | LCD_BS4 | LCD_BS5 | LCD_BS6 |
LCD_IU2 | LCD_IU3 | LCD_IU4 | LCD_IU5 | LCD_IU6 );
}
void LCDSetupGPIOs(P_XLLP_LCD_T pXllpLCD)
{
XLLP_UINT32_T LockID;
volatile XLLP_GPIO_T *p_GPIORegs;
p_GPIORegs = (XLLP_GPIO_T *) pXllpLCD->GPIO;
LockID = XllpLock(GPDR0);
if (pXllpLCD->DisplayType != LS022Q8DD06)
{
p_GPIORegs->GPDR0 = (p_GPIORegs->GPDR0 & ~XLLP_GPIO_BIT_L_VSYNC) | (XLLP_GPIO_BIT_PWM_OUT0 | XLLP_GPIO_BIT_L_CS);
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