📄 xlli_xsbase270_g_defs.inc
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;*********************************************************************************
;
; COPYRIGHT (c) 2002 - 2004 Intel Corporation
;
; The information in this file is furnished for informational use only,
; is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
;*********************************************************************************
;
; FILENAME: xlli_XSBASE270_G_defs.inc (Platform specific addresses and
; defalut values for XSBASE270_G platform bring up)
; NOTE: - This file has a def to configure xlli for MCP and non-MCP processors
;
; LAST MODIFIED: 13-Feb-2004
;
;******************************************************************************
;
;
; Include file for XSBASE270_G specific Cross Platform Low Level Initialization (XLLI)
;
;
; PLATFORM REGISTERS base address and register offsets from the base address
;
xlli_PLATFORM_REGISTERS EQU 0x0A000000
;
; Platform specific bits
;
xlli_SYS_RESET EQU (0x01) ; System reset bit
;
; platform GPIO pin settings (Bulverde/XSBASE270_G)
;
xlli_GPSR0_value EQU (0x00008000) ; Set registers
xlli_GPSR1_value EQU (0x00CF0002)
xlli_GPSR2_value EQU (0x0021C000)
xlli_GPSR3_value EQU (0x00000000)
xlli_GPCR0_value EQU (0x00200000) ; Clear registers
xlli_GPCR1_value EQU (0x00000380) ; FFUART related
xlli_GPCR2_value EQU (0x0)
xlli_GPCR3_value EQU (0x0)
xlli_GRER0_value EQU (0x0) ; Rising Edge Detect
xlli_GRER1_value EQU (0x0)
xlli_GRER2_value EQU (0x0)
xlli_GRER3_value EQU (0x0)
xlli_GFER0_value EQU (0x0) ; Falling Edge Detect
xlli_GFER1_value EQU (0x0)
xlli_GFER2_value EQU (0x0)
xlli_GFER3_value EQU (0x0)
xlli_GPLR0_value EQU (0x0) ; Pin Level Registers
xlli_GPLR1_value EQU (0x0)
xlli_GPLR2_value EQU (0x0)
xlli_GPLR3_value EQU (0x0)
xlli_GEDR0_value EQU (0x0) ; Edge Detect Status
xlli_GEDR1_value EQU (0x0)
xlli_GEDR2_value EQU (0x0)
xlli_GEDR3_value EQU (0x0)
xlli_GPDR0_value EQU (0x00208000) ; Direction Registers
xlli_GPDR1_value EQU (0x00CF0382)
xlli_GPDR2_value EQU (0x0021C000)
xlli_GPDR3_value EQU (0x00000000)
xlli_GAFR0_L_value EQU (0x80000000) ; Alternate function registers
xlli_GAFR0_U_value EQU (0x00000010)
xlli_GAFR1_L_value EQU (0x000A9558)
xlli_GAFR1_U_value EQU (0x000590AA)
xlli_GAFR2_L_value EQU (0xA0000000)
xlli_GAFR2_U_value EQU (0x00000402)
xlli_GAFR3_L_value EQU (0x00000000)
xlli_GAFR3_U_value EQU (0x00001400)
;
; MEMORY CONTROLLER SETTINGS FOR XSBASE270_G
;
xlli_MDREFR_value EQU (0x0000001E)
xlli_MSC0_value EQU (0x93C093C0) ; XSBASE270_G Board Flash value
;xlli_MSC1_value EQU (0xB884A691)
xlli_MSC1_value EQU (0xB88CA691) ;Change by Terry@2006-2-27 for 16 bits Networking
xlli_MSC2_value EQU (0x7FF4B88C)
xlli_MECR_value EQU (0x00000001)
xlli_MCMEM0_value EQU (0x00014307)
xlli_MCMEM1_value EQU (0x00014307)
xlli_MCATT0_value EQU (0x0001C787)
xlli_MCATT1_value EQU (0x0001C787)
xlli_MCIO0_value EQU (0x0001430F)
xlli_MCIO1_value EQU (0x0001430F)
xlli_FLYCNFG_value EQU (0x00000000)
xlli_MDMRSLP_value EQU (0x0000C008)
;xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
xlli_SXCNFG_value EQU (0x00007011)
RCR_VAL EQU 0x0000970C
RCR_COM1 EQU 0x00600060
RCR_COM2 EQU 0x00030003
RCR_COM3 EQU 0x00FF00FF
;
; Optimal values for MSCO for various MemClk frequencies are listed below
; These values are for K18 async flash
;
xlli_MSC0_13 EQU (0x12301230)
xlli_MSC0_19 EQU (0x12301230)
xlli_MSC0_26 EQU (0x12401240) ; 26 MHz setting
xlli_MSC0_32 EQU (0x12401240)
xlli_MSC0_39 EQU (0x13501350) ; 39 MHz setting
xlli_MSC0_45 EQU (0x13501350)
xlli_MSC0_52 EQU (0x13601360) ; 52 MHz setting
xlli_MSC0_58 EQU (0x13701370)
xlli_MSC0_65 EQU (0x13801380) ; 65 MHz setting
xlli_MSC0_68 EQU (0x13801380)
xlli_MSC0_71 EQU (0x14901490) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x14901490)
xlli_MSC0_78 EQU (0x14901490) ; 78 MHz setting
xlli_MSC0_81 EQU (0x14A014A0)
xlli_MSC0_84 EQU (0x14A014A0) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x14A014A0)
xlli_MSC0_91 EQU (0x14B014B0) ; 91 MHz setting
xlli_MSC0_94 EQU (0x14B014B0) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x14B014B0) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x15C015C0) ; 100.7 MHz setting
xlli_MSC0_104 EQU (0x15C015C0) ; 104 MHz setting
xlli_MSC0_110 EQU (0x15901590)
xlli_MSC0_117 EQU (0x15A015A0) ; 117 MHz setting
xlli_MSC0_124 EQU (0x15A015A0)
xlli_MSC0_130 EQU (0x15B015B0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x16B016B0)
xlli_MSC0_143 EQU (0x16C016C0)
xlli_MSC0_149 EQU (0x16C016C0)
xlli_MSC0_156 EQU (0x16C016C0)
xlli_MSC0_162 EQU (0x16C016C0)
xlli_MSC0_169 EQU (0x17D017D0) ; Given that the optimal value would be 13 (RDF), but according to B0 manual, it's different
xlli_MSC0_175 EQU (0x17C017C0)
xlli_MSC0_182 EQU (0x17C017C0)
xlli_MSC0_188 EQU (0x17D017D0)
xlli_MSC0_195 EQU (0x17E017E0)
xlli_MSC0_201 EQU (0x18E018E0)
xlli_MSC0_208 EQU (0x18E018E0)
; Now on a discrete XSBASE270_G platform with slightly better performing SDRAM
xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
xlli_DTC_39 EQU (0x00000000) ; 39 MHz setting
xlli_DTC_45 EQU (0x00000000) ; 45 MHz setting
xlli_DTC_52 EQU (0x00000000) ; 52 MHz setting
xlli_DTC_58 EQU (0x00000000) ; 58 MHz setting
xlli_DTC_65 EQU (0x00000000) ; 65 MHz setting
xlli_DTC_68 EQU (0x00000000) ; 68 MHz setting
xlli_DTC_71 EQU (0x00000000) ; 71 MHz setting
xlli_DTC_74 EQU (0x00000000) ; 74 MHz setting
xlli_DTC_78 EQU (0x00000000) ; 78 MHz setting
xlli_DTC_81 EQU (0x00000000) ; 81 MHz setting
xlli_DTC_84 EQU (0x00000000) ; 84 MHz setting
xlli_DTC_87 EQU (0x00000000) ; 87 MHz setting
xlli_DTC_91 EQU (0x00000000) ; 91 MHz setting
xlli_DTC_94 EQU (0x00000000) ; 94 MHz setting
xlli_DTC_97 EQU (0x00000000) ; 97 MHz setting
xlli_DTC_100 EQU (0x00000000) ; 100 MHz setting
xlli_DTC_104 EQU (0x02000200) ; 104 MHz setting
xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
xlli_DTC_130 EQU (0x01000100) ; 130 MHz setting - SDCLK Halved
xlli_DTC_136 EQU (0x01000100) ; 136 MHz setting - SDCLK Halved
xlli_DTC_143 EQU (0x01000100) ; 143 MHz setting - SDCLK Halved
xlli_DTC_149 EQU (0x01000100) ; 149 MHz setting - SDCLK Halved
xlli_DTC_156 EQU (0x01000100) ; 156 MHz setting - SDCLK Halved
xlli_DTC_162 EQU (0x01000100) ; 162 MHz setting - SDCLK Halved
xlli_DTC_169 EQU (0x01000100) ; 169 MHz setting - SDCLK Halved
xlli_DTC_175 EQU (0x01000100) ; 175 MHz setting - SDCLK Halved
xlli_DTC_182 EQU (0x02000200) ; 182 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_188 EQU (0x02000200) ; 188 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_195 EQU (0x02000200) ; 195 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_201 EQU (0x03000300) ; 201 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_208 EQU (0x03000300) ; 208 MHz setting - SDCLK Halved - Close to edge, so bump up
;
; Optimal values for DRI settings for various MemClk settings (MDREFR)
;
xlli_DRI_13 EQU (0x002) ; 13 MHz setting
xlli_DRI_19 EQU (0x003)
xlli_DRI_26 EQU (0x005) ; 26 MHz setting
xlli_DRI_32 EQU (0x006)
xlli_DRI_39 EQU (0x008) ; 39 MHz setting
xlli_DRI_45 EQU (0x00A)
xlli_DRI_52 EQU (0x00B) ; 52 MHz setting
xlli_DRI_58 EQU (0x00D)
xlli_DRI_65 EQU (0x00E) ; 65 MHz setting
xlli_DRI_68 EQU (0x00F)
xlli_DRI_71 EQU (0x010) ; 71 MHz setting
xlli_DRI_74 EQU (0x011)
xlli_DRI_78 EQU (0x012) ; 78 MHz setting
xlli_DRI_81 EQU (0x012)
xlli_DRI_84 EQU (0x013) ; 84 MHz setting
xlli_DRI_87 EQU (0x014)
xlli_DRI_91 EQU (0x015) ; 91 MHz setting
xlli_DRI_94 EQU (0x016) ; 94 MHz setting
xlli_DRI_97 EQU (0x016) ; 97 MHz setting
xlli_DRI_100 EQU (0x017) ; 100 MHz setting
xlli_DRI_104 EQU (0x018) ; 104 MHz setting
xlli_DRI_110 EQU (0x01A)
xlli_DRI_117 EQU (0x01B) ; 117 MHz setting
xlli_DRI_124 EQU (0x01D)
xlli_DRI_130 EQU (0x01E) ; 130 MHz setting
xlli_DRI_136 EQU (0x020)
xlli_DRI_143 EQU (0x021)
xlli_DRI_149 EQU (0x023)
xlli_DRI_156 EQU (0x025)
xlli_DRI_162 EQU (0x026)
xlli_DRI_169 EQU (0x028) ; 169 MHz setting
xlli_DRI_175 EQU (0x029)
xlli_DRI_182 EQU (0x02B)
xlli_DRI_188 EQU (0x02D)
xlli_DRI_195 EQU (0x02E)
xlli_DRI_201 EQU (0x030)
xlli_DRI_208 EQU (0x031) ; 208 MHz setting
xlli_MDCNFG_value EQU (0x000008C8) ; SDRAM Config Reg
xlli_MDMRS_value EQU (0x00000000) ; SDRAM Mode Reg Set Config Reg
;
; MEMORY PHYSICAL BASE ADDRESS(S)
;
xlli_SRAM_PHYSICAL_BASE EQU (0x5C000000) ; Physical base address for SRAM
xlli_SDRAM_PHYSICAL_BASE EQU (0xA0000000) ; Physical base address for SDRAM
;
; CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for XSBASE270_G
;
xlli_CCCR_value EQU (0x00000107) ; Bulverde (HW reset value to start)
;
; Clock Enable Register (CKEN) setting
;
xlli_CKEN_value EQU (0x00400200) ; Data to be set into the clock enable register
; bit 9 enables OS timers
; Bit 22 enables memory clock
;
; Address where system configuration data is stored
;
xlli_SCR_data EQU (0x5C03FFFC) ; Address in SRAM where system config data is stored
;
; Misc constants
;
xlli_MemSize_1Mb EQU (0x00100000)
IF :DEF: xlli_SDRAM_SIZE_32_MB
xlli_p_PageTable EQU (0xA1FFC000) ; Base address for memory Page Table (MCP version)
ELSE
xlli_p_PageTable EQU (0xA3FFC000) ; Base address for memory Page Table (Non-MCP version)
ENDIF
xlli_s_PageTable EQU (0x00004000) ; Page Table size (4K words - 16 Kb)
IF :DEF: POST_BUILD
xlli_v_xbBOOTROM EQU (0x04000000) ; (0x04000000 for POST)
ELSE
xlli_v_xbBOOTROM EQU (0x00000000)
ENDIF;
END
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