⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 fm1702.lst

📁 FM1702/rc500驱动代码 at89c55wd,汇编语言
💻 LST
📖 第 1 页 / 共 5 页
字号:
  000B               197      RegCollPos            data 0BH  ;!< bit position 
                             of the first bit
                     198                                      ;        collisio
                             n detected on the
                     199                                      ;        RF-inter
                             face
  000C               200      RegTimerValue         data 0CH  ;!< preload value
                              of the timer
  000D               201      RegCRCResultLSB       data 0DH  ;!< LSB of the CR
                             C Coprocessor register
  000E               202      RegCRCResultMSB       data 0EH  ;!< MSB of the CR
                             C Coprocessor register
  000F               203      RegBitFraming         data 0FH  ;!< Adjustments f
                             or bit oriented frames
                     204     ; PAGE 2      Transmitter and Coder Control
  0011               205      RegTxControl          data 11H  ;!< controls the 
                             logical behaviour of
                     206                                              ;!< the a
                             ntenna driver pins TX1 and TX2
  0012               207      RegCwConductance      data 12H  ;!< selects the c
                             onductance of the
                     208                                      ;        antenna 
                             driver pins TX1 and TX2
  0013               209      RFU13                 data 13H  ;!< RFU
  0014               210      RegCoderControl       data 14H  ;!< selects coder
                              rate
  0015               211      RegModWidth           data 15H  ;!< selects the w
                             idth of the
                     212                                      ;        modulati
                             on pulse
  0016               213      RFU16                 data 16H  ;!< RFU
A51 MACRO ASSEMBLER  FM1702                      10/31/2007 17:04:16 PAGE     5

  0017               214      RFU17                 data 17H  ;!< RFU
                     215     ; PAGE 3      Receiver and Decoder Control
  0019               216      RegRxControl1         data 19H  ;!< controls rece
                             iver behaviour
  001A               217      RegDecoderControl     data 1AH  ;!< controls deco
                             der behaviour
  001B               218      RegBitPhase           data 1BH  ;!< selets the bi
                             t phase between
                     219                                      ;        transmit
                             ter and receiver clock */
  001C               220      RegRxThreshold        data 1CH  ;!< selects thres
                             holds for the bit
                     221                                      ;        decoder 
                             */
  001D               222      RFU1D                 data 1DH  ;!< RFU
  001E               223      RegRxControl2         data 1EH  ;!< controls deco
                             der behaviour and
                     224                                      ;        defines 
                             the input source for the
                     225                                      ;        receiver
                              */
  001F               226      RegClockQControl      data 1FH  ;!< controls cloc
                             k generation for the
                     227                                      ;        90?phase
                              shifted Q-channel clock */
                     228     ; PAGE 4      RF-Timing and Channel Redundancy
  0021               229      RegRxWait             data 21H  ;!< selects the t
                             ime interval after
                     230                                      ;        transmis
                             sion, before receiver starts */
  0022               231      RegChannelRedundancy  data 22H  ;!< selects the k
                             ind and mode of
                     232                                      ;        checking
                              the data integrity on the
                     233                                      ;        RF-chann
                             el */
  0023               234      RegCRCPresetLSB       data 23H  ;!< LSB of the pr
                             e-set value for the
                     235                                      ;        CRC regi
                             ster */
  0024               236      RegCRCPresetMSB       data 24H  ;!< MSB of the pr
                             e-set value for the
                     237                                      ;        CRC regi
                             ster */
  0025               238      RFU25                 data 25H  ;!< RFU
  0026               239      RegMfOutSelect        data 26H  ;!< selects inter
                             nal signal applied to
                     240                                      ;        pin MfOu
                             t */
  0027               241      RFU27                 data 27H  ;!< RFU
                     242     ; PAGE 5      FIFO, Timer and IRQ-Pin Configuratio
                             n
  0029               243      RegFIFOLevel          data 29H  ;!< Defines level
                              for FIFO over- and
                     244                                      ;        underflo
                             w warning */
  002A               245      RegTimerClock         data 2AH  ;!< selects the d
                             ivider for the timer clock
  002B               246      RegTimerControl       data 2BH  ;!< selects start
                              and stop conditions
                     247                                      ;        for the 
                             timer */
  002C               248      RegTimerReload        data 2CH  ;!< defines the p
                             re-set value for the
A51 MACRO ASSEMBLER  FM1702                      10/31/2007 17:04:16 PAGE     6

                     249                                      ;        timer */
  002D               250      RegIRqPinConfig       data 2DH  ;!< configures th
                             e output stage of
                     251                                      ;        pin IRq 
                             */
  002E               252      RFU2E                 data 2EH  ;!< RFU
  002F               253      RFU2F                 data 2FH  ;!< RFU
                     254     ; PAGE 6      RFU
  0031               255      RFU31                 data 31H  ;!< RFU
  0032               256      RFU32                 data 32H  ;!< RFU
  0033               257      RFU33                 data 33H  ;!< RFU
  0034               258      RFU34                 data 34H  ;!< RFU
  0035               259      RFU35                 data 35H  ;!< RFU
  0036               260      RFU36                 data 36H  ;!< RFU
  0037               261      RFU37                 data 37H  ;!< RFU
                     262     ; PAGE 7      Test Control
  0039               263      RFU39                 data 39H  ;!< RFU
  003A               264      RegTestAnaSelect      data 3AH  ;!< selects analo
                             g test mode
  003B               265      RFU3B                 data 3BH  ;!< RFU
  003C               266      RFU3C                 data 3CH  ;!< RFU
  003D               267      RegTestDigiSelect     data 3DH  ;!< selects digit
                             al test mode
  003E               268      RFU3E                 data 3EH  ;!< RFU
  003F               269      RegTestDigiAccess     data 3FH
                     270     
                     271     
                     272      ;DEF_FIFO_LENGTH       data 64   ;!< default FIFO
                              size
                     273     ; maximal transfer buffer size between PCD and PIC
                             C
  0100               274      MAX_RF_BUF_SIZE       data 256
                     275     
                     276     ;                   P C D - C O M M A N D S
  0000               277      PCD_IDLE           data 00H ;!< No action: cancel
                              current command
                     278                                         ;   or home st
                             ate */
  0001               279      PCD_WRITEE2        data 01H ;!< Get data from FIF
                             O and write it to the E2PROM
  0003               280      PCD_READE2         data 03H ;!< Read data from E2
                             PROM and put it into the
                     281                                         ;   FIFO */
  0007               282      PCD_LOADCONFIG     data 07H ;!< Read data from E2
                             PROM and initialise the
                     283                                         ;   registers 
                             */
  000B               284      PCD_LOADKEYE2      data 0BH ;!< Read a master key
                              from the E2PROM and put
                     285                                         ;   it into th
                             e master key buffer */
  000C               286      PCD_AUTHENT1       data 0CH ;!< Perform the first
                              part of the card
                     287                                         ;   authentica
                             tion using the Crypto1 algorithm.
                     288     
                     289                                     ;Remark: The maste
                             r key is automatically taken
                     290                                     ;from the master k
                             ey buffer. this implies,
                     291                                     ;that the command 
                             LoadKeyE2 has to be executed
                     292                                     ;before using a ce
                             rtain key for card
A51 MACRO ASSEMBLER  FM1702                      10/31/2007 17:04:16 PAGE     7

                     293                                     ;authentication */
  0012               294      PCD_CALCCRC        data 12H ;!< Activate the CRC-
                             Coprocessor
                     295     
                     296                                     ;Remark: The resul
                             t of the CRC calculation can
                     297                                     ;be read from the 
                             register CRCResultXXX */
  0014               298      PCD_AUTHENT2       data 14H ;!< Perform the secon
                             d part of the card
                     299                                         ;   authentica
                             tion using the Crypto1 algorithm. */
  0016               300      PCD_RECEIVE        data 16H ;!< Activate Receiver
                              Circuitry. Before the
                     301                                         ;   receiver a
                             ctually starts, the state machine
                     302                                         ;   waits unti
                             l the time configured in the
                     303                                         ;   register R
                             xWait has passed.
                     304     
                     305                                     ;Remark: It is pos
                             sible to read any received
                     306                                     ;data from the FIF
                             O while the Receive command
                     307                                     ;is active. Thus i
                             t is possible to receive an
                     308                                     ;unlimited number 
                             of bytes by reading them
                     309                                     ;from the FIFO in 
                             timer. */
  0019               310      PCD_LOADKEY        data 19H ;!< Read a master key
                              from the FIFO and put it
                     311                                         ;   into the m
                             aster key buffer
                     312     
                     313                                     ;Remark: The maste
                             r key has to be prepared in
                     314                                     ;a certain format.
                              Thus, 12 byte have to be
                     315                                     ;passed to load a 
                             6 byte master key */
  001A               316      PCD_TRANSMIT       data 1AH ;!< Transmit data fro
                             m FIFO to the card
                     317     
                     318                                     ;Remark: If data i
                             s already in the FIFO when
                     319                                     ;the command is ac
                             tivated, this data is
                     320                                     ;transmitted immed
                             iately. It is possible to
                     321                                     ;write data to the
                              FIFO while the Transmit
                     322                                     ;command is active
                             . Thus it is possible to
                     323                                     ;transmit an unlim
                             ited number of bytes in one
                     324                                     ;stream by writtin
                             g them to the FIFO in time.*/
  001E               325      PCD_TRANSCEIVE     data 1EH ;!< Transmits data fr
                             om FIFO to the card and
                     326                                         ;   after that
                              automatically activates the
                     327                                         ;   receiver. 
A51 MACRO ASSEMBLER  FM1702                      10/31/2007 17:04:16 PAGE     8

                             Before the receiver actually

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -