📄 fm1702.asm
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RESET_WDT bit p2.6
LED bit p2.0;p2.5
BEEP bit p1.0;p2.4
RC500RST bit P3.5
;BEEP bit p1.1
;LED bit p1.3
;RC500RST bit P1.2
ParallelPort equ P1
ParallelA bit p3.3
ParallelB bit p3.4
RC500INT_EN bit EX0
RC500_BASE data 20h
LED_BIT bit 06h
BEEP_BIT bit 05h
RSTW_BIT bit 04h
FLAG_T2OUT bit 08h
FLAG_RCV bit 09h
FLAG_T0OUT bit 0ah
FLAG_HAVECARD bit 0bh
FLAG_CARDSN bit 0ch
FLAG_PARALLEL bit 0dh
FLAG_SECOND bit 0eh
FLAG_HALFSEC bit 0fh
FLAG_IDLE bit 10h
FLAG_CARD bit 11h
FLAG_CSTART bit 12h
AUTH_MODE data 24h
ATQ_BUF data 25h ;25h--26h(2Bytes)
SAK_BUF data 27h ;27h(1Byte)
;/ struct definition for a communication channel between function and ISR
MfCmdInfo data 28h ;34h--3bh(8Bytes)
MfCmd data 28h
MfStatus data 29h
MfBytesSend data 2ah
MfBytesToSend data 2bh
MfBytesReceived data 2ch
MfBitsReceived data 2dh
MfIrqSource data 2eh
MfCollPos data 2fh
MLastSelectedSnr data 30h ;30h--33h(4Byres)
SNR_BUF data 34h ;34h--37h(4Bytes)
RC500_SNR data 38h ;38h--3bh(4Bytes)
;UID_BUF data 50h ;50h--59h(10Bytes)
STATUS data 3ch
T2CNTL data 3dh
T2CNTH data 3eh
T0CNT data 3fh
RCV_LEN data 40h
SND_LEN data 41h
SR_MODE data 42h
CHK_CNT data 43h
BLOCK data 44h
SECTOR data 45h
SND_BUF data 048h ;048h--06fh(40Bytes)
RCV_BUF data 070h ;070h--09fh(48Bytes)
RCV_QUEUE data 0a0h ;0a0h--0afh(16Bytes)
KEYS_BUF data 0b0h ;0b0h--0bbh(12Bytes)
SND_QUEUE data 0beh ;0beh--0cfh(18Bytes)
STACK data 0d0h ;0d0h--0ffh(48Byte)
;RCBaseAddress data 07f00h
;FIFO length of the reader IC
DEF_FIFO_LENGTH data 64 ;!< default FIFO size
MFIFOLength equ DEF_FIFO_LENGTH
MAX_CHECK equ 20
;fosc=11.0592MHz
TH0_10ms equ 0DCh
TL0_10ms equ 000h
TH0_1ms equ 0FCh
TL0_1ms equ 068h
T1_9600 equ 0fdh
TH2_50us equ 0FFh
TL2_50us equ 0D2h
TH2_1ms equ 0FCh
TL2_1ms equ 068h
TH2_10ms equ 0DCh
TL2_10ms equ 003h
COMM_HEAD equ 07eh
COMM_SHIFT equ 07dh
SHIFT_SHIFT equ 0dh
SHIFT_HEAD equ 0eh
CMD_SEEK equ 10h
CMD_IDLE equ 01h
CMD_CARDSN equ 02h
CMD_KEY equ 03h
CMD_KEYEE equ 04h
CMD_READBLOCK equ 05h
CMD_READBLOCKEE equ 06h
CMD_WRITEBLOCK equ 07h
CMD_WRITEBLOCKEE equ 08h
CMD_READAUTH equ 09h
CMD_READAUTHEE equ 0ah
CMD_WRITEAUTH equ 0bh
CMD_WRITEAUTHEE equ 0ch
RNUM_CMD_SEEK equ 1
RNUM_CMD_IDLE equ 1
RNUM_CMD_CARDSN equ 1
RNUM_CMD_KEY equ 7
RNUM_CMD_KEYEE equ 9
RNUM_CMD_READBLOCK equ 4
RNUM_CMD_READBLOCKEE equ 4
RNUM_CMD_WRITEBLOCK equ 20
RNUM_CMD_WRITEBLOCKEE equ 20
RNUM_CMD_READAUTH equ 3
RNUM_CMD_READAUTHEE equ 3
RNUM_CMD_WRITEAUTH equ 19
RNUM_CMD_WRITEAUTHEE equ 19
SNUM_CMD_SEEK equ 5
SNUM_CMD_IDLE equ 1
SNUM_CMD_CARDSN equ 5
SNUM_CMD_KEY equ 1
SNUM_CMD_KEYEE equ 2
SNUM_CMD_READBLOCK_OK equ 17
SNUM_CMD_READBLOCK_FALSE equ 2
SNUM_CMD_READBLOCKEE_OK equ 17
SNUM_CMD_READBLOCKEE_FALSE equ 2
SNUM_CMD_WRITEBLOCK equ 2
SNUM_CMD_WRITEBLOCKEE equ 2
SNUM_CMD_READAUTH_OK equ 17
SNUM_CMD_READAUTH_FALSE equ 2
SNUM_CMD_READAUTHEE_OK equ 17
SNUM_CMD_READAUTHEE_FALSE equ 2
SNUM_CMD_WRITEAUTH equ 2
SNUM_CMD_WRITEAUTHEE equ 2
KEY_A equ 00
KEY_B equ 01
SR_IDLE equ 00h
SR_SEND equ 01h
SR_RECEIVE equ 02h
; RCAP2_50us 65536L - OSC_FREQ/240417L
; RCAP2_1ms 65536L - OSC_FREQ/12021L
; RCAP2_10ms 65536L - OSC_FREQ/1200L
; 8052 Extensions
T2CON DATA 0C8H
RCAP2L DATA 0CAH
RCAP2H DATA 0CBH
TL2 DATA 0CCH
TH2 DATA 0CDH
MAX_RCV equ 48
; 8052 Extensions
; IE
ET2 BIT 0ADH
; IP
PT2 BIT 0BDH
; P1
T2EX BIT 91H
T2 BIT 90H
; T2CON
TF2 BIT 0CFH
EXF2 BIT 0CEH
RCLK BIT 0CDH
TCLK BIT 0CCH
EXEN2 BIT 0CBH
TR2 BIT 0CAH
C_T2 BIT 0C9H
CP_RL2 BIT 0C8H
; PAGE 0 Command and Status
RegPage data 00H ;!< Page Select Register
RegCommand data 01H ;!< Command Register
RegFIFOData data 02H ;!< FiFo Register
RegPrimaryStatus data 03H ;!< Modem State/IRQ/ERR/LoHiAlert Reg
RegFIFOLength data 04H ;!< Buffer length Register
RegSecondaryStatus data 05H ;!< diverse status flags
RegInterruptEn data 06H ;!< IRQ enable Register
RegInterruptRq data 07H ;!< IRQ bits Register
; PAGE 1 Control and Status
RegControl data 09H ;!< processor control
RegErrorFlag data 0AH ;!< error flags showing the error
; status of the last command executed
RegCollPos data 0BH ;!< bit position of the first bit
; collision detected on the
; RF-interface
RegTimerValue data 0CH ;!< preload value of the timer
RegCRCResultLSB data 0DH ;!< LSB of the CRC Coprocessor register
RegCRCResultMSB data 0EH ;!< MSB of the CRC Coprocessor register
RegBitFraming data 0FH ;!< Adjustments for bit oriented frames
; PAGE 2 Transmitter and Coder Control
RegTxControl data 11H ;!< controls the logical behaviour of
;!< the antenna driver pins TX1 and TX2
RegCwConductance data 12H ;!< selects the conductance of the
; antenna driver pins TX1 and TX2
RFU13 data 13H ;!< RFU
RegCoderControl data 14H ;!< selects coder rate
RegModWidth data 15H ;!< selects the width of the
; modulation pulse
RFU16 data 16H ;!< RFU
RFU17 data 17H ;!< RFU
; PAGE 3 Receiver and Decoder Control
RegRxControl1 data 19H ;!< controls receiver behaviour
RegDecoderControl data 1AH ;!< controls decoder behaviour
RegBitPhase data 1BH ;!< selets the bit phase between
; transmitter and receiver clock */
RegRxThreshold data 1CH ;!< selects thresholds for the bit
; decoder */
RFU1D data 1DH ;!< RFU
RegRxControl2 data 1EH ;!< controls decoder behaviour and
; defines the input source for the
; receiver */
RegClockQControl data 1FH ;!< controls clock generation for the
; 90?phase shifted Q-channel clock */
; PAGE 4 RF-Timing and Channel Redundancy
RegRxWait data 21H ;!< selects the time interval after
; transmission, before receiver starts */
RegChannelRedundancy data 22H ;!< selects the kind and mode of
; checking the data integrity on the
; RF-channel */
RegCRCPresetLSB data 23H ;!< LSB of the pre-set value for the
; CRC register */
RegCRCPresetMSB data 24H ;!< MSB of the pre-set value for the
; CRC register */
RFU25 data 25H ;!< RFU
RegMfOutSelect data 26H ;!< selects internal signal applied to
; pin MfOut */
RFU27 data 27H ;!< RFU
; PAGE 5 FIFO, Timer and IRQ-Pin Configuration
RegFIFOLevel data 29H ;!< Defines level for FIFO over- and
; underflow warning */
RegTimerClock data 2AH ;!< selects the divider for the timer clock
RegTimerControl data 2BH ;!< selects start and stop conditions
; for the timer */
RegTimerReload data 2CH ;!< defines the pre-set value for the
; timer */
RegIRqPinConfig data 2DH ;!< configures the output stage of
; pin IRq */
RFU2E data 2EH ;!< RFU
RFU2F data 2FH ;!< RFU
; PAGE 6 RFU
RFU31 data 31H ;!< RFU
RFU32 data 32H ;!< RFU
RFU33 data 33H ;!< RFU
RFU34 data 34H ;!< RFU
RFU35 data 35H ;!< RFU
RFU36 data 36H ;!< RFU
RFU37 data 37H ;!< RFU
; PAGE 7 Test Control
RFU39 data 39H ;!< RFU
RegTestAnaSelect data 3AH ;!< selects analog test mode
RFU3B data 3BH ;!< RFU
RFU3C data 3CH ;!< RFU
RegTestDigiSelect data 3DH ;!< selects digital test mode
RFU3E data 3EH ;!< RFU
RegTestDigiAccess data 3FH
;DEF_FIFO_LENGTH data 64 ;!< default FIFO size
; maximal transfer buffer size between PCD and PICC
MAX_RF_BUF_SIZE data 256
; P C D - C O M M A N D S
PCD_IDLE data 00H ;!< No action: cancel current command
; or home state */
PCD_WRITEE2 data 01H ;!< Get data from FIFO and write it to the E2PROM
PCD_READE2 data 03H ;!< Read data from E2PROM and put it into the
; FIFO */
PCD_LOADCONFIG data 07H ;!< Read data from E2PROM and initialise the
; registers */
PCD_LOADKEYE2 data 0BH ;!< Read a master key from the E2PROM and put
; it into the master key buffer */
PCD_AUTHENT1 data 0CH ;!< Perform the first part of the card
; authentication using the Crypto1 algorithm.
;Remark: The master key is automatically taken
;from the master key buffer. this implies,
;that the command LoadKeyE2 has to be executed
;before using a certain key for card
;authentication */
PCD_CALCCRC data 12H ;!< Activate the CRC-Coprocessor
;Remark: The result of the CRC calculation can
;be read from the register CRCResultXXX */
PCD_AUTHENT2 data 14H ;!< Perform the second part of the card
; authentication using the Crypto1 algorithm. */
PCD_RECEIVE data 16H ;!< Activate Receiver Circuitry. Before the
; receiver actually starts, the state machine
; waits until the time configured in the
; register RxWait has passed.
;Remark: It is possible to read any received
;data from the FIFO while the Receive command
;is active. Thus it is possible to receive an
;unlimited number of bytes by reading them
;from the FIFO in timer. */
PCD_LOADKEY data 19H ;!< Read a master key from the FIFO and put it
; into the master key buffer
;Remark: The master key has to be prepared in
;a certain format. Thus, 12 byte have to be
;passed to load a 6 byte master key */
PCD_TRANSMIT data 1AH ;!< Transmit data from FIFO to the card
;Remark: If data is already in the FIFO when
;the command is activated, this data is
;transmitted immediately. It is possible to
;write data to the FIFO while the Transmit
;command is active. Thus it is possible to
;transmit an unlimited number of bytes in one
;stream by writting them to the FIFO in time.*/
PCD_TRANSCEIVE data 1EH ;!< Transmits data from FIFO to the card and
; after that automatically activates the
; receiver. Before the receiver actually
; starts,the state machine waits until the
; time configured in the register RxWait has
; passed.
;Remark: This command is the combination of
;Transmit and Receive.*/
PCD_RESETPHASE data 3FH ;!< Runs the Reset- and Initialisation Phase
;Remark: This command can not be activated by
;software, but only by a Power-On or
;Hard Reset */
; General Include File for serveral defines concerning conditional library
; compilation and microcontroller usage
;#include "OsDefs.h"
PICC_REQIDL data 026H ;!< request idle
PICC_REQALL data 052H ;!< request all
PICC_ANTICOLL1 data 093H ;!< anticollision level 1 106 kBaud
PICC_ANTICOLL2 data 095H ;!< anticollision level 2
PICC_ANTICOLL3 data 097H ;!< anticollision level 3
PICC_AUTHENT1A data 060H ;!< authentication using key A
PICC_AUTHENT1B data 061H ;!< authentication using key B
PICC_READ data 030H ;!< read block
PICC_WRITE data 0A0H ;!< write block
PICC_DECREMENT data 0C0H ;!< decrement value
PICC_INCREMENT data 0C1H ;!< increment value
PICC_RESTORE data 0C2H ;!< restore command code
PICC_TRANSFER data 0B0H ;!< transfer command code
PICC_HALT data 050H ;!< halt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Reader Error Codes Base Address Start: 0000
; Base Address End: -999
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
READER_ERR_BASE_START data 0
MI_OK data 0
MI_CHK_OK data 0
MI_CRC_ZERO data 0
MI_CRC_NOTZERO data 1
MI_NOTAGERR data -1
MI_CHK_FAILED data -1
MI_CRCERR data -2
MI_CHK_COMPERR data -2
MI_EMPTY data -3
MI_AUTHERR data -4
MI_PARITYERR data -5
MI_CODEERR data -6
MI_SERNRERR data -8
MI_KEYERR data -9
MI_NOTAUTHERR data -10
MI_BITCOUNTERR data -11
MI_BYTECOUNTERR data -12
MI_IDLE data -13
MI_TRANSERR data -14
MI_WRITEERR data -15
MI_INCRERR data -16
MI_DECRERR data -17
MI_READERR data -18
MI_OVFLERR data -19
MI_POLLING data -20
MI_FRAMINGERR data -21
MI_ACCESSERR data -22
MI_UNKNOWN_COMMAND data -23
MI_COLLERR data -24
MI_RESETERR data -25
MI_INITERR data -25
MI_INTERFACEERR data -26
MI_ACCESSTIMEOUT data -27
MI_NOBITWISEANTICOLL data -28
MI_QUIT data -30
MI_RECBUF_OVERFLOW data -50
MI_SENDBYTENR data -51
MI_SENDBUF_OVERFLOW data -53
MI_BAUDRATE_NOT_SUPPORTED data -54
MI_SAME_BAUDRATE_REQUIRED data -55
MI_WRONG_PARAMETER_VALUE data -60
MI_BREAK data -99
MI_NY_IMPLEMENTED data -100
MI_NO_MFRC data -101
MI_MFRC_NOTAUTH data -102
MI_WRONG_DES_MODE data -103
MI_HOST_AUTH_FAILED data -104
MI_WRONG_LOAD_MODE data -106
MI_WRONG_DESKEY data -107
MI_MKLOAD_FAILED data -108
MI_FIFOERR data -109
MI_WRONG_ADDR data -110
MI_DESKEYLOAD_FAILED data -111
MI_WRONG_SEL_CNT data -114
MI_WRONG_TEST_MODE data -117
MI_TEST_FAILED data -118
MI_TOC_ERROR data -119
MI_COMM_ABORT data -120
MI_INVALID_BASE data -121
MI_MFRC_RESET data -122
MI_WRONG_VALUE data -123
MI_VALERR data -124
org 0000h
sjmp main
org 0003h
ljmp SingleResponseIsr
org 000bh
ljmp Timer0Out
org 0013h
ljmp ParallelReceive
org 0023h
ljmp SerialReceive
org 002bh
ljmp Timer2Out
org 0050h
main:
mov sp,#STACK
mov r0,#20h
mov r7,#0e0h
mn_00:
mov @r0,#0
inc r0
djnz r7,mn_00
mov RC500_BASE,#7fh
setb IT0
setb IT1
setb PS
setb PX1
setb EA
lcall LEDOn
mov TMOD,#21h
mov TH1,#T1_9600
mov TL1,#T1_9600
mov TH0,#TH0_10ms
mov TL0,#TL0_10ms
orl PCON,#80h
setb TR1
clr ET1
setb TR0
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