📄 stm32f10x_tim.c
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* peripheral.
* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
* that contains the configuration information for the specified
* TIM peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= CCER_CC2E_Reset;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= CCMR_OC24M_Mask;
/* Select the Output Compare Mode */
tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
/* Reset the Output Polarity level */
tmpccer &= CCER_CC2P_Reset;
/* Set the Output Compare Polarity */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
/* Set the Output State */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
/* Set the Capture Compare Register value */
TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
{
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= CCER_CC2NP_Reset;
/* Set the Output N Polarity */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
/* Reset the Output N State */
tmpccer &= CCER_CC2NE_Reset;
/* Set the Output N State */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
/* Reset the Ouput Compare and Output Compare N IDLE State */
tmpcr2 &= CR2_OIS2_Reset;
tmpcr2 &= CR2_OIS2N_Reset;
/* Set the Output Idle state */
tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
/* Set the Output N Idle state */
tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
}
/*******************************************************************************
* Function Name : TIM_OC3Init
* Description : Initializes the TIMx Channel3 according to the specified
* parameters in the TIM_OCInitStruct.
* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
* peripheral.
* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
* that contains the configuration information for the specified
* TIM peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= CCER_CC3E_Reset;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= CCMR_OC13M_Mask;
/* Select the Output Compare Mode */
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
/* Reset the Output Polarity level */
tmpccer &= CCER_CC3P_Reset;
/* Set the Output Compare Polarity */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
/* Set the Output State */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
/* Set the Capture Compare Register value */
TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
{
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= CCER_CC3NP_Reset;
/* Set the Output N Polarity */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
/* Reset the Output N State */
tmpccer &= CCER_CC3NE_Reset;
/* Set the Output N State */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
/* Reset the Ouput Compare and Output Compare N IDLE State */
tmpcr2 &= CR2_OIS3_Reset;
tmpcr2 &= CR2_OIS3N_Reset;
/* Set the Output Idle state */
tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
/* Set the Output N Idle state */
tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
}
/*******************************************************************************
* Function Name : TIM_OC4Init
* Description : Initializes the TIMx Channel4 according to the specified
* parameters in the TIM_OCInitStruct.
* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
* peripheral.
* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
* that contains the configuration information for the specified
* TIM peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC4E Bit */
TIMx->CCER &= CCER_CC4E_Reset;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= CCMR_OC24M_Mask;
/* Select the Output Compare Mode */
tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
/* Reset the Output Polarity level */
tmpccer &= CCER_CC4P_Reset;
/* Set the Output Compare Polarity */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12);
/* Set the Output State */
tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12);
/* Set the Capture Compare Register value */
TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
{
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Ouput Compare IDLE State */
tmpcr2 &= CR2_OIS4_Reset;
/* Set the Output Idle state */
tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6);
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
}
/*******************************************************************************
* Function Name : TIM_ICInit
* Description : Initializes the TIM peripheral according to the specified
* parameters in the TIM_ICInitStruct.
* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
* peripheral.
* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
* that contains the configuration information for the specified
* TIM peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
{
/* TI1 Configuration */
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
/* Set the Input Capture Prescaler value */
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
}
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
{
/* TI2 Configuration */
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
/* Set the Input Capture Prescaler value */
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
}
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
{
/* TI3 Configuration */
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
/* Set the Input Capture Prescaler value */
TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
}
else
{
/* TI4 Configuration */
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
/* Set the Input Capture Prescaler value */
TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
}
}
/*******************************************************************************
* Function Name : TIM_PWMIConfig
* Description : Configures the TIM peripheral according to the specified
* parameters in the TIM_ICInitStruct to measure an external PWM
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