📄 2440init.s
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nop
1: b 1b @ infinite loop
#=============================================================================================
# ARM core's exception entry
#=============================================================================================
.align
HandlerFIQ: HANDLER HandleFIQ
HandlerIRQ: HANDLER HandleIRQ
HandlerUndef: HANDLER HandleUndef
HandlerSWI: HANDLER HandleSWI
HandlerDabort: HANDLER HandleDabort
HandlerPabort: HANDLER HandlePabort
IsrIRQ:
sub sp,sp,#4 @ reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
on_the_ram:
# Initialize stacks
# bl InitStacks @ if SVCstack is initialized before
#=============================================================================================
# InitStacks, initializing stacks of different mode
# Don't use DRAM operation, such as stmfd,ldmfd......
# 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
#=============================================================================================
InitStacks:
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 @ UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 @ AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 @ IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 @ FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 @ SVCMode
ldr sp,=SVCStack
# USER mode has not be initialized.
# mov pc,lr @ The LR register won't be valid if the current mode is not SVC mode.
# Setup IRQ handler
ldr r0,=HandleIRQ @ This routine is needed
ldr r1,=IsrIRQ @ if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
# Copy and paste RW data/zero initialized data
ldr r0, = Image_RO_Limit@ Get pointer to ROM data
ldr r1, = Image_RW_Base @ and RAM copy
ldr r3, = Image_ZI_Base
# Zero init base => top of initialised data
cmp r0, r1 @ Check that they are different
beq F2
F1:
cmp r1, r3 @ Copy init data
ldrcc r2, [r0], #4 @ --> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r1], #4 @ --> STRCC r2, [r1] + ADD r1, r1, #4
bcc F1
F2:
ldr r1, = Image_ZI_Limit @ Top of zero init segment
mov r2, #0
B5:
cmp r3, r1 @ Zero init
strcc r2, [r3], #4
bcc B5
MRS r0, CPSR
BIC r0, r0, #0x80 @ IRQ enable
MSR CPSR_cxsf, r0
mov fp, #0 @ no previous frame, so fp=0
mov a2, #0 @ set argv to NULL
bl Main @ call Main
mov pc, #0
#=============================================================================================
#SMRDATA
# Memory configuration should be optimized for best performance
# The following parameter is not optimized.
# Memory access cycle parameter strategy
# 1) The memory settings is safe parameters even at HCLK=75Mhz.
# 2) SDRAM refresh period is for HCLK=75Mhz.
#=============================================================================================
.ltorg
SMRDATA:
.long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) @ GCS0
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) @ GCS1
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) @ GCS2
.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) @ GCS3
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) @ GCS4
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) @ GCS5
.long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) @ GCS6
.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @ GCS7
.long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)
.long 0xB1 @ SCLK power saving mode, BANKSIZE 128M/128M
.long 0x20 @ MRSR6 CL=3clk
.long 0x20 @ MRSR7
.ifdef CONFIG_S3C2410_NAND_BOOT
@
@ copy_myself: copy bootloader to ram
@
copy_myself:
mov r10, lr
@port configuration for NAND
ldr r1, =GPACON
ldr r2, [r1,#0]
bic r2, r2, #0x3f
orr r2, r2, #0x3f
str r2, [r1]
@ reset NAND 复位NAND
@TACLS=7 TWRPH0=7 TWRPH1=7
ldr r1, =NFCONF
.ifeq NAND_SUMSANG - 1
ldr r2, =((7<<12)|(7<<8)|(7<<4)|(1<<3)|(1<<2)|(0<<0)) @ initial value
.endif
.ifeq NAND_SUMSANG - 2
ldr r2, =((7<<12)|(7<<8)|(7<<4)|(1<<3)|(1<<2)|(1<<1)|(0<<0)) @ initial value
.endif
str r2, [r1, #0]
ldr r1, =NFCONT
ldr r2, =((0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0))
str r2, [r1, #0]
ldr r1, =NFSTAT
ldr r2, =0x0
str r2, [r1, #0]
ldr r1, =NFCONT
ldr r2, [r1, #0]
bic r2, r2, #0x2 @ enable chip
str r2, [r1, #0]
ldr r1, =NFSTAT
ldr r2, [r1]
orr r2, r2, #(1<<2)
str r2, [r1, #0] @clear RB
ldr r1, =NFCMD
mov r2, #0xff @ RESET command
strb r2, [r1, #0]
mov r3, #0 @ wait
1: add r3, r3, #0x1
cmp r3, #0x20
blt 1b
ldr r1, =NFSTAT
2: ldr r2, [r1, #0] @ wait ready
tst r2, #0x4
beq 2b
ldr r1, =NFCONT
ldr r2, [r1, #0]
orr r2, r2, #0x2 @ disable chip
str r2, [r1, #0]
@ get read to call C functions (for nand_read())
@ ldr sp, DW_STACK_START @ setup stack pointer
@ mov fp, #0 @ no previous frame, so fp=0
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 @ SVCMode
ldr sp,=SVCStack
@ copy to RAM
ldr r0, =RAM_BASE @ RAM_BASE
mov r4, #0x0 @ start sector
mov r5, #0x20000 @ bootloader size(128K)
@ bl nand_read_ll
@===============
ldr r1, =NFCONT
ldr r2, [r1, #0]
bic r2, r2, #0x2 @ enable chip
str r2, [r1, #0]
ldr r1, =NFSTAT
ldr r2, [r1]
orr r2, r2, #(1<<2)
str r2, [r1, #0] @clear RB
@for(i = start_addr; i<(start_addr+size);)
LOOP:
ldr r1, =NFCMD
mov r2, #0x00 @ read command
strb r2, [r1, #0]
mov r3, #0 @ wait
1: add r3, r3, #0x1
cmp r3, #0x30
blt 1b
@ NF_ADDR(0x00);
ldr r1, =NFADDR
mov r2, #0x00
strb r2, [r1,#0]
@ NF_ADDR(0x00);
ldr r1, =NFADDR
mov r2, #0x00
str r2, [r1,#0]
@ NF_ADDR((i) & 0xff);
ldr r1, =NFADDR
and r2, r4, #0xff
str r2, [r1,#0]
@ NF_ADDR((i >> 8) & 0xff);
ldr r1, =NFADDR
mov r2, r4, LSR #8
and r2, r2,#0xff
str r2, [r1,#0]
.ifeq NAND_SUMSANG - 2
@ NF_ADDR((i >> 16) & 0xff);
ldr r1, =NFADDR
mov r2, r4, LSR #16
and r2, r2,#0xff
str r2, [r1,#0]
.endif
@ NF_CMD(0x30); // Read command 2nd
ldr r1, =NFCMD
mov r2, #0x30 @ Read command 2nd
str r2, [r1, #0]
mov r3, #0 @ wait
1: add r3, r3, #0x1
cmp r3, #0x30
blt 1b
@ NF_DETECT_RB(); // wait tR(max 12us)
ldr r1, =NFSTAT
2: ldr r2, [r1, #0] @ wait ready
tst r2, #0x4
beq 2b
mov r3, #0 @ wait
1: add r3, r3, #0x1
cmp r3, #0x30
blt 1b
__RdPage2048:
stmfd sp!,{r1-r11}
ldr r1,=0x4e000010 @NFDATA
mov r2,#0x800
RD2:
LDR4STR1 r1,r4,r3
LDR4STR1 r1,r5,r3
LDR4STR1 r1,r6,r3
LDR4STR1 r1,r7,r3
LDR4STR1 r1,r8,r3
LDR4STR1 r1,r9,r3
LDR4STR1 r1,r10,r3
LDR4STR1 r1,r11,r3
stmia r0!,{r4-r11}
subs r2,r2,#32
bne RD2
ldmfd sp!,{r1-r11}
@ add r0, r0,#0x800
add r4, r4, #0x1
subs r5,r5, #0x800
bne LOOP
@==============
tst r0, #0x0
beq ok_nand_read
.ifdef CONFIG_DEBUG_LL
bad_nand_read:
ldr r0, STR_FAIL
ldr r1, SerBase
bl PrintWord
1: b 1b @ infinite loop
.endif
ok_nand_read:
.ifdef CONFIG_DEBUG_LL
ldr r0, STR_OK
ldr r1, SerBase
bl PrintWord
.endif
@ verify
mov r0, #0
ldr r1, =RAM_BASE
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq done_nand_read
bne go_next
notmatch:
.ifdef CONFIG_DEBUG_LL
sub r0, r0, #4
ldr r1, SerBase
bl PrintHexWord
ldr r0, STR_FAIL
ldr r1, SerBase
bl PrintWord
.endif
1: b 1b
done_nand_read:
.ifdef CONFIG_DEBUG_LL
ldr r0, STR_OK
ldr r1, SerBase
bl PrintWord
.endif
mov pc, r10
@ clear memory
@ r0: start address
@ r1: length
mem_clear:
mov r2, #0
mov r3, r2
mov r4, r2
mov r5, r2
mov r6, r2
mov r7, r2
mov r8, r2
mov r9, r2
clear_loop:
stmia r0!, {r2-r9}
subs r1, r1, #(8 * 4)
bne clear_loop
mov pc, lr
#.else @ CONFIG_S3C2410_NAND_BOOT
#.ifdef EXEC_FROM_RAM
# ldr r0,=ROM_BASE
# ldr r1,=Image_RO_Base
# ldr r3,=Image_ZI_Limit
#LoopRw:
# cmp r1, r3
# ldrcc r2, [r0], #4
# strcc r2, [r1], #4
# bcc LoopRw
#
# ldr pc, =Jump
#Jump:
# nop
# nop
# nop
#.endif
.endif
#=======================================================================================================================
# ARM core's exception and user interrupt handler store address
# The address may be different between the different assemble after link.
#=============================================================================================
.align
.equ HandleReset, _ISR_STARTADDRESS
.equ HandleUndef, _ISR_STARTADDRESS+4
.equ HandleSWI, _ISR_STARTADDRESS+4*2
.equ HandlePabort, _ISR_STARTADDRESS+4*3
.equ HandleDabort, _ISR_STARTADDRESS+4*4
.equ HandleReserved, _ISR_STARTADDRESS+4*5
.equ HandleIRQ, _ISR_STARTADDRESS+4*6
.equ HandleFIQ, _ISR_STARTADDRESS+4*7
#Don't use the label 'IntVectorTable',
#The value of IntVectorTable is different with the address you think it may be.
#IntVectorTable
@;@0x33FF_FF20
.equ HandleEINT0, _ISR_STARTADDRESS+4*8
.equ HandleEINT1, _ISR_STARTADDRESS+4*9
.equ HandleEINT2, _ISR_STARTADDRESS+4*10
.equ HandleEINT3, _ISR_STARTADDRESS+4*11
.equ HandleEINT4_7, _ISR_STARTADDRESS+4*12
.equ HandleEINT8_23, _ISR_STARTADDRESS+4*13
.equ HandleCAM, _ISR_STARTADDRESS+4*14
.equ HandleBATFLT, _ISR_STARTADDRESS+4*15
.equ HandleTICK, _ISR_STARTADDRESS+4*16
.equ HandleWDT, _ISR_STARTADDRESS+4*17
.equ HandleTIMER0, _ISR_STARTADDRESS+4*18
.equ HandleTIMER1, _ISR_STARTADDRESS+4*19
.equ HandleTIMER2, _ISR_STARTADDRESS+4*20
.equ HandleTIMER3, _ISR_STARTADDRESS+4*21
.equ HandleTIMER4, _ISR_STARTADDRESS+4*22
.equ HandleUART2, _ISR_STARTADDRESS+4*23
@;@0x33FF_FF60
.equ HandleLCD, _ISR_STARTADDRESS+4*24
.equ HandleDMA0, _ISR_STARTADDRESS+4*25
.equ HandleDMA1, _ISR_STARTADDRESS+4*26
.equ HandleDMA2, _ISR_STARTADDRESS+4*27
.equ HandleDMA3, _ISR_STARTADDRESS+4*28
.equ HandleMMC, _ISR_STARTADDRESS+4*29
.equ HandleSPI0, _ISR_STARTADDRESS+4*30
.equ HandleUART1, _ISR_STARTADDRESS+4*31
.equ HandleNFCON, _ISR_STARTADDRESS+4*32
.equ HandleUSBD, _ISR_STARTADDRESS+4*33
.equ HandleUSBH, _ISR_STARTADDRESS+4*34
.equ HandleIIC, _ISR_STARTADDRESS+4*35
.equ HandleUART, _ISR_STARTADDRESS+4*36
.equ HandleSPI1, _ISR_STARTADDRESS+4*37
.equ HandleRTC, _ISR_STARTADDRESS+4*38
.equ HandleADC, _ISR_STARTADDRESS+4*39
.end
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