📄 2440init.s
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#=======================================================================================================================
# File Name : 2440init.s
# Author : embest
# Descript : S3C2410x system start up codes
# Configure memory, ISR ,stacks
# Initialize C-variables
# History :
# (1) R.X.Huang, Programming modify, March 12, 2005
#=======================================================================================================================
.include "option.inc"
.include "memcfg.inc"
.include "2440addr.inc"
#.equ CONFIG_S3C2410_NAND_BOOT , 1
# 1 ----- K9F1G08U0A
# 2 ----- K9K8G08U0A
.equ NAND_SUMSANG , 2
/*------------------------------------------------------------------------------------------*/
/* constant define */
/*------------------------------------------------------------------------------------------*/
.equ BIT_SELFREFRESH, (1<<22)
.equ USERMODE, 0x10
.equ FIQMODE, 0x11
.equ IRQMODE, 0x12
.equ SVCMODE, 0x13
.equ ABORTMODE, 0x17
.equ UNDEFMODE, 0x1b
.equ MODEMASK, 0x1f
.equ NOINT, 0xc0
.equ CPSR_IRQ_EN, 0x80 /* */
.equ CPSR_IRQ_MASK, 0x40 /* disable Interrupt Mode (IRQ) */
.equ CPSR_FIQ_MASK, 0x80 /* disable Fast Interrupt Mode (FIQ) */
.equ R1_iA, (1<<31)
.equ R1_nF, (1<<30)
#The location of stacks
.equ UserStack , (_STACK_BASEADDRESS-0x3800) @0x33ff4800 ~
.equ SVCStack , (_STACK_BASEADDRESS-0x2800) @0x33ff5800 ~
.equ UndefStack , (_STACK_BASEADDRESS-0x2400) @0x33ff5c00 ~
.equ AbortStack , (_STACK_BASEADDRESS-0x2000) @0x33ff6000 ~
.equ IRQStack , (_STACK_BASEADDRESS-0x1000) @0x33ff7000 ~
.equ FIQStack , (_STACK_BASEADDRESS-0x0) @0x33ff8000 ~
.equ SDRAM_BASE , 0x30200000
.equ RAM_BASE , 0x30000000
.equ SDRAM_CLEAR , 0x0
.equ SDRAM_TEST , 0x12345678
.equ SDRAM_SIZE , 0x07ff0000
################################################
# Test Sleep&Wakeup 0
################################################
.equ DCACHE_LINES_PER_SET_BITS , 6
.equ DCACHE_LINES_PER_SET , 64
.equ DCACHE_NUM_SETS , 8
.equ DCACHE_SET_INDEX_BIT , (32-DCACHE_LINES_PER_SET_BITS)
.equ DCACHE_LINE_SIZE , 32
.equ SLEEPDATA_BASE_VIRTUAL , 0xAC024000
.equ SLEEPDATA_BASE_PHYSICAL , 0x30024000
.equ WORD_SIZE , 4
.equ SleepState_Data_Start , (0)
.equ SleepState_WakeAddr , (SleepState_Data_Start )
.equ SleepState_MMUCTL , (SleepState_WakeAddr + WORD_SIZE )
.equ SleepState_MMUTTB , (SleepState_MMUCTL + WORD_SIZE )
.equ SleepState_MMUDOMAIN , (SleepState_MMUTTB + WORD_SIZE )
.equ SleepState_SVC_SP , (SleepState_MMUDOMAIN + WORD_SIZE )
.equ SleepState_SVC_SPSR , (SleepState_SVC_SP + WORD_SIZE )
.equ SleepState_FIQ_SPSR , (SleepState_SVC_SPSR + WORD_SIZE )
.equ SleepState_FIQ_R8 , (SleepState_FIQ_SPSR + WORD_SIZE )
.equ SleepState_FIQ_R9 , (SleepState_FIQ_R8 + WORD_SIZE )
.equ SleepState_FIQ_R10 , (SleepState_FIQ_R9 + WORD_SIZE )
.equ SleepState_FIQ_R11 , (SleepState_FIQ_R10 + WORD_SIZE )
.equ SleepState_FIQ_R12 , (SleepState_FIQ_R11 + WORD_SIZE )
.equ SleepState_FIQ_SP , (SleepState_FIQ_R12 + WORD_SIZE )
.equ SleepState_FIQ_LR , (SleepState_FIQ_SP + WORD_SIZE )
.equ SleepState_ABT_SPSR , (SleepState_FIQ_LR + WORD_SIZE )
.equ SleepState_ABT_SP , (SleepState_ABT_SPSR + WORD_SIZE )
.equ SleepState_ABT_LR , (SleepState_ABT_SP + WORD_SIZE )
.equ SleepState_IRQ_SPSR , (SleepState_ABT_LR + WORD_SIZE )
.equ SleepState_IRQ_SP , (SleepState_IRQ_SPSR + WORD_SIZE )
.equ SleepState_IRQ_LR , (SleepState_IRQ_SP + WORD_SIZE )
.equ SleepState_UND_SPSR , (SleepState_IRQ_LR + WORD_SIZE )
.equ SleepState_UND_SP , (SleepState_UND_SPSR + WORD_SIZE )
.equ SleepState_UND_LR , (SleepState_UND_SP + WORD_SIZE )
.equ SleepState_SYS_SP , (SleepState_UND_LR + WORD_SIZE )
.equ SleepState_SYS_LR , (SleepState_SYS_SP + WORD_SIZE )
.equ SleepState_Data_End , (SleepState_SYS_LR + WORD_SIZE )
.equ SLEEPDATA_SIZE , (SleepState_Data_End - SleepState_Data_Start)/4
.equ MMU_CTL_MASK , 0x3FFF0000
.equ MMU_TTB_MASK , 0x00003FFF
.equ MMU_ID_MASK , 0xFFFFFFF0
################################################
# End Test Sleep&Wakeup 0
################################################
.macro HANDLER HandleLabel
sub sp,sp,#4 /* decrement sp(to store jump address) */
stmfd sp!,{r0} /* PUSH the work register to stack(lr does't push because it return to original address) */
ldr r0,=\HandleLabel /* load the address of HandleXXX to r0 */
ldr r0,[r0] /* load the contents(service routine start address) of HandleXXX */
str r0,[sp,#4] /* store the contents(ISR) of HandleXXX to stack */
ldmfd sp!,{r0,pc} /* POP the work register and pc(jump to ISR) */
.endm
.MACRO LDR4STR1 src,tmp1,tmp2
ldrb \tmp1,[\src]
ldrb \tmp2,[\src]
orr \tmp1,\tmp1,\tmp2,LSL #8
ldrb \tmp2,[\src]
orr \tmp1,\tmp1,\tmp2,LSL #16
ldrb \tmp2,[\src]
orr \tmp1,\tmp1,\tmp2,LSL #24
.ENDM
.extern Image_RO_Base
.extern Image_RO_Limit /* End of ROM code (=start of ROM data) */
.extern Image_RW_Base /* Base of RAM to initialise */
.extern Image_ZI_Base /* Base and limit of area */
.extern Image_ZI_Limit /* to zero initialise */
.extern Main /* The main entry of mon program */
#=============================================================================================
# reset entry point
#=============================================================================================
.text
ENTRY:
b ResetHandler
b HandlerUndef @ handler for Undefined mode
b HandlerSWI @ handler for SWI interrupt
b HandlerPabort @ handler for PAbort
b HandlerDabort @ handler for DAbort
b . @ reserved
b HandlerIRQ @ handler for IRQ interrupt
b HandlerFIQ @ handler for FIQ interrupt
#- 0x20
@ Power-off the CPU.
str r1, [r0] @ enable SDRAM self-refresh.
mov r1,#16 @ Wait until self-refresh is issued,which may not be needed.
ramloop1:
subs r1,r1,#1
bne ramloop1
str r3, [r2] @ MISCCR setting.
str r5, [r4] @ POWER OFF!!!!!
b .
#=============================================================================================
# ResetHandler
#=============================================================================================
ResetHandler:
# Make sure that TLB & cache are consistent
mov r0, #0x0
mcr p15, 0, r0, c8, c7, 0 @ flush both TLB
mcr p15, 0, r0, c7, c5, 0 @ invalidate instruction cache
mcr p15, 0, r0, c7, c6, 0 @ invalidate data cache
# set L3Mode output 0
ldr r0,=GPBCON
ldr r1,[r0]
bic r1,r1,#(3<<4)
orr r1,r1,#(1<<4)
str r1,[r0]
ldr r0,=GPBDAT
ldr r1,[r0]
bic r1,r1,#(1<<2)
str r1,[r0]
ldr r0,=GPBUP
ldr r1,[r0]
orr r1,r1,#(1<<2)
str r1,[r0]
# set eint0 output 1
ldr r0,=GPFCON
ldr r1,[r0]
orr r1,r1,#(1<<0)
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,[r0]
orr r1,r1,#(1<<0)
str r1,[r0]
ldr r0,=GPFUP
ldr r1,[r0]
orr r1,r1,#(1<<0)
str r1,[r0]
# Make sure GPF0 stabilization
mov r0, #0x200
loop200:
subs r0, r0, #1
bne loop200
# set the VDD_EN as output and as high
ldr r0, =GPACON
ldr r1,[r0]
bic r1, r1, #(1<<16) @ ngcs1-5 as output(111 1110 1111 1111 1111 1111)12-16
str r1, [r0]
ldr r0, =GPADAT
ldr r1, [r0] @ ldr r1, = 0x7e0fff
orr r1, r1, #(1 << 16) @ VDD33_EN output 1
str r1,[r0]
# Make sure GPA16 stabilization
mov r0, #0x200
loop1200:
subs r0, r0, #1
bne loop1200
# this must after GPA16 stabilization
@ ldr r0, =GPFUP
@ ldr r1, =0x01
@ str r1, [r0]
ldr r0,=GPFCON
ldr r1,[r0]
bic r1,r1,#(3<<0)
str r1,[r0]
ldr r0,=WTCON @ watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0xffffffff @ all interrupt disable
str r1,[r0]
ldr r0,=INTSUBMSK
ldr r1,=0x7ff @ all sub interrupt disable
str r1,[r0]
ldr r0, = INTMOD
mov r1, #0x0 @ set all interrupt as IRQ (not FIQ)
str r1, [r0]
ldr r1, =MISCCR @ MISCCR's Bit [22:20] -> 100
ldr r0, [r1]
bic r0, r0, #(7 << 20)
orr r0, r0, #(4 << 20)
str r0, [r1]
#Added for confirm clock divide for 2440
#setting value Fclk:Hclk:Pclk 1:3:6
ldr r0,=CLKDIVN
ldr r1,=0x7
str r1,[r0]
ands r1,r1,#0xe @ Make AsyncBusMode
beq jump10
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF|R1_iA
mcr p15, 0, r0, c1, c0, 0
jump10:
# To reduce PLL lock time, adjust the LOCKTIME register.
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]
#Configure UPLL
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
str r1,[r0]
nop @ Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
# Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) @ Fin=16.9MHz,Fout=400MHz
str r1,[r0]
mov r0, #0x2000
loop3000:
subs r0, r0, #1
bne loop3000
#################################################
# BEGIN: Power Management #
#################################################
# Check if the boot is caused by the wake-up from POWER_OFF mode.
ldr r1, =GSTATUS2 @ Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2
beq WATCHDOG_RESET @ if not wakeup from PowerOffmode Skip
b WAKEUP_SLEEP @ if wakeup from PowerOff mode
@goto Power-up code.
@Watchdog reset
WATCHDOG_RESET:
tst r10, #0x4 @ In case of the wake-up from Watchdog reset,
@ go to SDRAM start address(0x3000_0000)
b StartPointAfterSleepWakeUp @ If not wakeup from Watchdog reset,
# beq %F4 @ If not wakeup from Watchdog reset,
@ goto Normal Mode.
mov r0, #4
str r0, [r1] @ Clear the GSTATUS2. Because same code is located in memory address.
# Set memory control registers
add r0, pc, #SMRDATA - (. + 8)
ldr r1, =BWSCON @ BWSCON Address
add r2, r0, #52 @ End address of SMRDATA
loop20:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop20
mov r1, #512
loop21:
subs r1, r1, #1 @ wait until the SelfRefresh is released.
bne loop21
ldr r2, =0x201000 @ offset into the RAM
add r2, r2, #0x30000000 @ add physical base
mov pc, r2 @ & jump to StartUp address
nop
nop
nop
b .
#Case of Power off reset
WAKEUP_SLEEP:
ldr r1, =MISCCR @ MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1] @ I don't know why, Just fallow Sample Code.
bic r0, r0, #(3 << 17) @ SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0, [r1]
#####################################################
# Add for Power Management #
#####################################################
#=============================================================================================
# StartPointAfterSleepWakeUp
#=============================================================================================
.global StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp:
# Set memory control registers
add r0, pc, #SMRDATA - (. + 8)
ldr r1, =BWSCON @ BWSCON Address
add r2, r0, #52 @ End address of SMRDATA
loop22:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop22
tst r10, #0x2 @ Power-Off reset check
beq BRINGUP_WINCE @ Normal Mode Booting
#Recover Process : Starting Point
RECOVER_PROCESS:
ldr r1, =GSTATUS2 @ Determine Booting Mode
ldr r10, [r1]
str r10, [r1] @ Clear Booting Mode
# 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL @ pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 @ pointer for checksum calculation
mov r2, #0
ldr r0, =SLEEPDATA_SIZE @ get size of data structure to do checksum on
B40:
ldr r1, [r3], #4 @ pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1 @ dec the count
bne B40 @ loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] @ get the Sleep data checksum from the Power Manager Scratch pad register
teq r2, r3 @ compare to what we saved before going to sleep
# bne BringUpWinCE @ bad news - do a cold boot - If emergency power off case, normal booting.
bne JumpToRAM @ bad news - do a cold boot - If emergency power off case, normal booting.
b MMUENABLE
JumpToRAM:
ldr r2, =0x201000 @ offset into the RAM
ldr r3, =0x30000000 @ add physical base
add r2, r2, r3
mov pc, r2 @ & jump to StartUp address
MMUENABLE:
@ 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] @ load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] @ load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] @ load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr] @ load the LR address
nop
nop
nop
nop
nop
# if software reset
mov r1, #0x38000000
teq r1, r7
bne F10
bl BRINGUP_WINCE
#wakeup routine
F10:
mcr p15, 0, r10, c3, c0, 0 @ setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 @ PT address
mcr p15, 0, r0, c8, c7, 0 @ flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 @ restore MMU control
# 3. Jump to Kernel Image's fw.s(Awake_address)
mov pc, r7 @ & jump to new virtual address (back up Power management stack)
nop
BRINGUP_WINCE:
#set sp
ldr sp, =SVCStack
.ifdef CONFIG_S3C2410_NAND_BOOT
bl copy_myself
.endif
@ jump to ram
ldr r1, =on_the_ram
add pc, r1, #0
nop
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