option.inc

来自「Embest IDE下s3c2440的测试工程」· INC 代码 · 共 176 行

#===========================================
# NAME: OPTION.A
# DESC: Configuration options for .S files
# HISTORY:
# 02.28.2002: ver 0.0
# 03.11.2003: ver 0.0	attached for 2440.
# jan E, 2004: ver0.03  modified for 2440A01.
#===========================================


#Start address of each stacks,
.equ	_STACK_BASEADDRESS	, 0x37ff8000
.equ	_MMUTT_STARTADDRESS	, 0x37ff8000
.equ	_ISR_STARTADDRESS	, 0x37ffff00


	
@	.global THUMBCODE
@ 	.equ   THUMBCODE,  TRUE
@	.equ	THUMBCODE,  FALSE

		
		.global 	PLL_ON_START
		.equ		PLL_ON_START,	1
@PLL_ON_START	SETL 	{TRUE}


		.global	ENDIAN_CHANGE
@ENDIAN_CHANGE	SETL	{FALSE}
		.equ	ENDIAN_CHANGE,		0

		.global	ENTRY_BUS_WIDTH
@ENTRY_BUS_WIDTH	SETA	16
		.equ	ENTRY_BUS_WIDTH,	16


#BUSWIDTH = 16,32
		.global    BUSWIDTH	@max. bus width for the GPIO configuration
		.equ		BUSWIDTH,	32
@BUSWIDTH	SETA    32

		.global	UCLK
		.equ	UCLK,	48000000
@UCLK	SETA	48000000

		.global	XTAL_SEL
		.global	FCLK
		.global	CPU_SEL

#(1) Select CPU 	
#CPU_SEL	SETA	32440000	@ 32440000:2440X.
@CPU_SEL SETA	32440001	@ 32440001:2440A
.equ	CPU_SEL ,	32440001
#(2) Select XTaL
#XTAL_SEL	SETA	12000000
@XTAL_SEL	SETA	16934400
.equ	XTAL_SEL	,	16934400
#(3) Select FCLK
@FCLK		SETA	304000000
@FCLK		SETA	296352000
.equ	FCLK,	399651840		
@(4) Select Clock Division (Fclk:Hclk:Pclk)
.equ	CLKDIV_VAL	,	7	@ 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
			


.if (XTAL_SEL == 12000000)
	.if (FCLK == 271500000)
		.equ	M_MDIV		,	173		@Fin=12.0MHz Fout=271.5MHz
		.equ	M_PDIV		,	2
		.if (CPU_SEL == 32440001)
			.equ	M_SDIV		,	2		@ 2440A
   		.else
			.equ	M_SDIV		,	1		@ 2440X
   		.endif
	.endif
	
	.if (FCLK == 304000000)
		.equ	M_MDIV		,	68		@Fin=12.0MHz Fout=304.8MHz
		.equ	M_PDIV		,	1
		.if CPU_SEL = 32440001
			.equ	M_SDIV		,	1		@ 2440A
		.else
			.equ	M_SDIV		,	0		@ 2440X
		.endif
	.endif


	.if (UCLK == 48000000)
		.equ	U_MDIV		,	56		@Fin=12.0MHz Fout=48MHz
		.equ	U_PDIV		,	2
		.equ	U_SDIV		,	2
	.endif
	.if (UCLK == 96000000)
		.equ	U_MDIV		,	56		@Fin=12.0MHz Fout=96MHz
		.equ	U_PDIV		,	2
		.equ	U_SDIV		,	1
	.endif

.else	@ else if XTAL_SEL = 16.9344Mhz

	.if (FCLK == 266716800)
		.equ	M_MDIV		,	118	@Fin=16.9344MHz
		.equ	M_PDIV		,	2
		.if (CPU_SEL == 32440001)
			.equ	M_SDIV		,	2		@ 2440A
		.else
			.equ	M_SDIV		,	1		@ 2440X
		.endif
	.endif
	
	.if (FCLK == 399651840)
		.equ	M_MDIV		,	110	@Fin=16.9344MHz
		.equ	M_PDIV		,	3
		.if (CPU_SEL == 32440001)
			.equ	M_SDIV		,	1		@ 2440A
		.else
			.equ	M_SDIV		,	0		@ 2440X
		.endif
	.endif

	.if (FCLK == 296352000)
		.equ	M_MDIV		,	97	@Fin=16.9344MHz
		.equ	M_PDIV		,	1
		.if (CPU_SEL == 32440001)
			.equ	M_SDIV		,	2		@ 2440A
		.else
			.equ	M_SDIV		,	1		@ 2440X
		.endif
	.endif
	.if (FCLK == 541900800)
		.equ	M_MDIV		,	120	@Fin=16.9344MHz
		.equ	M_PDIV		,	2
		.if (CPU_SEL == 32440001)
			.equ	M_SDIV		,	1		@ 2440A
		.else
			.equ	M_SDIV		,	0		@ 2440X
		.endif
	.endif
	
	.if (UCLK == 48000000)
		.equ	U_MDIV		,	60	@Fin=16.9344MHz Fout=48MHz
		.equ	U_PDIV		,	4
		.equ	U_SDIV		,	2
	.endif
	.if (UCLK == 96000000)
		.equ	U_MDIV		,	60	@Fin=16.9344MHz Fout=96MHz
		.equ	U_PDIV		,	4
		.equ	U_SDIV		,	1
	.endif
	
.endif	@ end of if XTAL_SEL = 12000000.

#*******************************************************************************
#* Macro Name     : MOV_PC_LR
#* Description    : lr -> pc without mode change
#* Input          : none
#* Output         : none
#*******************************************************************************
.macro MOV_PC_LR
	.ifdef THUMBCODE
		bx      lr
	.else
		mov     pc,lr
	.endif
.endm

.macro MOVEQ_PC_LR
	.ifdef THUMBCODE
		bxeq      lr
	.else
		moveq     pc,lr
	.endif
.endm