📄 nand.c
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#endif
Uart_Printf("[block #%d is marked as a bad block]\n",block);
return OK;
}
static NF8_ReadPage(U32 block, U32 page, U8 *buffer)
{
int i;
unsigned int blockPage;
U32 Mecc, Secc,Necc;
U8 *bufPt=buffer;
U8 se[16], ecc0, ecc1, ecc2, ecc3,a,b,c,d,e;
#if (ID_NAND == ID_K9F1G08U0A)
blockPage=(block<<6)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command 1st
NF_ADDR(0); // Column = 0
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_CMD(0x30); // Read command 2nd
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage2048(bufPt);
#endif
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
Necc = NF_RDDATA(); // read 4~7
NF8_Spare_Data[4]=Necc&0xff;
NF8_Spare_Data[5]=(Necc&0xff00)>>8;
NF8_Spare_Data[6]=(Necc&0xff0000)>>16;
NF8_Spare_Data[7]=(Necc&0xff000000)>>24;
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
for(a = 12; a<64;a++)
{
ecc1= NF_RDDATA8();
NF8_Spare_Data[a] = ecc1;
}
NF_nFCE_H();
#elif ID_NAND == ID_K9K8G08U0A
blockPage=(block<<6)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command 1st
NF_ADDR(0); // Column = 0
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff);
NF_CMD(0x30); // Read command 2nd
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage2048(bufPt);
#endif
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
Necc = NF_RDDATA(); // read 4~7
NF8_Spare_Data[4]=Necc&0xff;
NF8_Spare_Data[5]=(Necc&0xff00)>>8;
NF8_Spare_Data[6]=(Necc&0xff0000)>>16;
NF8_Spare_Data[7]=(Necc&0xff000000)>>24;
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
for(a = 12; a<64;a++)
{
ecc1= NF_RDDATA8();
NF8_Spare_Data[a] = ecc1;
}
NF_nFCE_H();
#elif ID_NAND == ID_K9S1208V0M
blockPage=(block<<5)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff); //
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage512(bufPt);
#endif
/*
NF_MECC_Lock();
rNFMECCD0=NF_RDDATA();
NF_nFCE_H();
if ((rNFESTAT0&0x3) == 0x0) return OK;
else return FAIL;
*/
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
NF_RDDATA(); // read 4~7
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
NF_nFCE_H();
#endif
if ((rNFESTAT0&0xf) == 0x0){
Uart_Printf("#");
return OK;
}
else {
Uart_Printf("!");
return FAIL;
}
}
int NF8_ReadPage2(U32 block,U32 page,U8 *buffer)
{
int i;
unsigned int blockPage;
U32 Mecc, Secc,Necc;
U8 *bufPt=buffer;
U8 se[16], ecc0, ecc1, ecc2, ecc3,a,b,c,d,e;
#if (ID_NAND == ID_K9F1G08U0A)
blockPage=(block<<6)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command 1st
NF_ADDR(0); // Column = 0
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_CMD(0x30); // Read command 2nd
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage2048(bufPt);
#endif
NF_MECC_Lock();
/*
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
Necc = NF_RDDATA(); // read 4~7
NF8_Spare_Data[4]=Necc&0xff;
NF8_Spare_Data[5]=(Necc&0xff00)>>8;
NF8_Spare_Data[6]=(Necc&0xff0000)>>16;
NF8_Spare_Data[7]=(Necc&0xff000000)>>24;
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
for(a = 12; a<64;a++)
{
ecc1= NF_RDDATA8();
NF8_Spare_Data[a] = ecc1;
}
*/
NF_nFCE_H();
#elif ID_NAND == ID_K9K8G08U0A
blockPage=(block<<6)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command 1st
NF_ADDR(0); // Column = 0
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff);
NF_CMD(0x30); // Read command 2nd
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage2048(bufPt);
#endif
NF_MECC_Lock();
/*
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
Necc = NF_RDDATA(); // read 4~7
NF8_Spare_Data[4]=Necc&0xff;
NF8_Spare_Data[5]=(Necc&0xff00)>>8;
NF8_Spare_Data[6]=(Necc&0xff0000)>>16;
NF8_Spare_Data[7]=(Necc&0xff000000)>>24;
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
for(a = 12; a<64;a++)
{
ecc1= NF_RDDATA8();
NF8_Spare_Data[a] = ecc1;
}
*/
NF_nFCE_H();
#elif ID_NAND == ID_K9S1208V0M
blockPage=(block<<5)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff); //
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage512(bufPt);
#endif
/*
NF_MECC_Lock();
rNFMECCD0=NF_RDDATA();
NF_nFCE_H();
if ((rNFESTAT0&0x3) == 0x0) return OK;
else return FAIL;
*/
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
NF_RDDATA(); // read 4~7
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
NF_nFCE_H();
#endif
/* if ((rNFESTAT0&0xf) == 0x0){
Uart_Printf("#");
return OK;
}
else {
Uart_Printf("!");
return FAIL;
}
*/
return OK;
}
static int NF8_WritePage(U32 block,U32 page,U8 *buffer)
{
int i;
U32 blockPage, Mecc, Secc;
U8 *bufPt=buffer;
#if USE_NFINIT
NFConDone=0;
rNFCONT|=(1<<9);
rNFCONT|=(1<<10);
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
#endif
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
#if ID_NAND == ID_K9F1G08U0A
blockPage=(block<<6)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column = 0
NF_ADDR(0); // Column 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & page num.
for(i=0;i<2048;i++) {
NF_WRDATA8(*bufPt++); // Write one page to NFM from buffer
}
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [0] [1] [2] [3] x [Bad marking] SECC0 SECC1
Mecc = rNFMECC0;
se8Buf[0]=(U8)(Mecc&0xff);
se8Buf[1]=(U8)((Mecc>>8) & 0xff);
se8Buf[2]=(U8)((Mecc>>16) & 0xff);
se8Buf[3]=(U8)((Mecc>>24) & 0xff);
se8Buf[5]=0xff; // Marking good block
NF_SECC_UnLock();
//Write extra data(ECC, bad marking)
for(i=0;i<4;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Main ECC)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_SECC_Lock();
Secc=rNFSECC;
se8Buf[8]=(U8)(Secc&0xff);
se8Buf[9]=(U8)((Secc>>8) & 0xff);
for(i=4;i<64;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Spare ECC and Mark)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
#if USE_NFINIT
while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
#else
NF_DETECT_RB();
#endif
if(rNFSTAT&0x8) return FAIL; // soft lock or tight lock
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