mg84fl54.h

基於Full Speed USB Controller 1T 8051的SPI控制源程序

/*--------------------------------------------------------
MEGAWIN MG84FL54B.h
Header file for Megawin 80C52 microcontrollers 
Release on 12/2007 
--------------------------------------------------------*/

/*  Standard 8051 Byte Registers  */
sfr P0    = 0x80;
sfr SP    = 0x81;
sfr DPL   = 0x82;
sfr DPH   = 0x83;
sfr PCON  = 0x87;
sfr TCON  = 0x88;
sfr TMOD  = 0x89;
sfr TL0   = 0x8A;
sfr TL1   = 0x8B;
sfr TH0   = 0x8C;
sfr TH1   = 0x8D;
sfr P1    = 0x90;
sfr SCON  = 0x98;
sfr SBUF  = 0x99;
sfr P2    = 0xA0;
sfr IE    = 0xA8;
sfr P3    = 0xB0;
sfr IP    = 0xB8;
sfr PSW   = 0xD0;
sfr ACC   = 0xE0;
sfr B     = 0xF0;

/*---------------------------------------------------------
New-defined SFRs
----------------------------------------------------------*/

/* MPC84FL(E)xx extension */
sfr AUXR    = 0x8E;
sfr P1M0    = 0x91;
sfr P1M1    = 0x92;
sfr P0M0    = 0x93;
sfr P0M1    = 0x94;
sfr P2M0    = 0x95;
sfr P2M1    = 0x96;
sfr AUXR2  = 0xA6;     
sfr TSTWD   = 0xA7;     
sfr SADDR   = 0xA9;
sfr AUXIE   = 0xAD;    
sfr AUXIP    = 0xAE;    
sfr P3M0    = 0xB1;
sfr P3M1    = 0xB2;
sfr P4M0    = 0xB3;     
sfr P4M1    = 0xB4;    
sfr XICON   = 0xC0;   
sfr T2CON   = 0xC8;   
sfr T2MOD   = 0xC9;  
sfr RCAP2L  = 0xCA;  
sfr RCAP2H  = 0xCB; 
sfr TL2     = 0xCC;     
sfr TH2     = 0xCD;   
sfr SADEN   = 0xB9;
sfr CKCON2  = 0xBF;
sfr CKCON   = 0xC7;
sfr SIADR   = 0xD1;
sfr SIDAT   = 0xD2;
sfr SISTA   = 0xD3;
sfr KBPATN  = 0xD5;    
sfr KBCON   = 0xD6; 
sfr KBMASK  = 0xD7;
sfr WDTCR   = 0xE1;
sfr P4      = 0xE8;    

/* for SPI Function only */

sfr SPISTAT = 0x84; 
sfr SPICTL  = 0x85;  
sfr SPIDAT  = 0x86; 

/* for ISP Function only */

sfr IFD     = 0xE2;
sfr IFADRH  = 0xE3;
sfr IFADRL  = 0xE4;
sfr SCMD    = 0xE6;
sfr ISPCR   = 0xE7;
sfr SICON      = 0xF8;

/*  BIT Registers  */

/* Port 0 (80H) */

sbit P0_7   = P0^7;
sbit P0_6   = P0^6;
sbit P0_5   = P0^5;
sbit P0_4   = P0^4;
sbit P0_3   = P0^3;
sbit P0_2   = P0^2;
sbit P0_1   = P0^1;
sbit P0_0   = P0^0;

sbit KBI7   = P0^7;
sbit KBI6   = P0^6;
sbit KBI5   = P0^5;
sbit KBI4   = P0^4;
sbit KBI3   = P0^3;
sbit KBI2   = P0^2;
sbit KBI1   = P0^1;
sbit KBI0   = P0^0;


/*  TCON (88H) */

sbit TF1    = TCON^7;
sbit TR1    = TCON^6;
sbit TF0    = TCON^5;
sbit TR0    = TCON^4;
sbit IE1    = TCON^3;
sbit IT1    = TCON^2;
sbit IE0    = TCON^1;
sbit IT0    = TCON^0;

/*  Port 1 (90H) */

sbit P1_7   = P1^7;
sbit P1_6   = P1^6;
sbit P1_5   = P1^5;
sbit P1_4   = P1^4;
sbit P1_3   = P1^3;
sbit P1_2   = P1^2;
sbit P1_1   = P1^1;
sbit P1_0   = P1^0;

/* Port 2 (A0H) */

sbit SPICLK = P2^7;
sbit MISO   = P2^6;
sbit MOSI   = P2^5;
sbit SS        = P2^4;
sbit SDA    = P2^1;
sbit SCL     = P2^0;

sbit P2_7   = P2^7;
sbit P2_6   = P2^6;
sbit P2_5   = P2^5;
sbit P2_4   = P2^4;
sbit P2_3   = P2^3;
sbit P2_2   = P2^2;
sbit P2_1   = P2^1;
sbit P2_0   = P2^0;


/*  SCON (98H) */

sbit SM0    = SCON^7;
sbit FE     = SCON^7;
sbit SM1    = SCON^6;
sbit SM2    = SCON^5;
sbit REN    = SCON^4;
sbit TB8    = SCON^3;
sbit RB8    = SCON^2;
sbit TI     = SCON^1;
sbit RI     = SCON^0;


/*  IE (A8H) */

sbit EA    = IE^7;
sbit ET2   = IE^5;
sbit ES    = IE^4;
sbit ET1   = IE^3;
sbit EX1   = IE^2;
sbit ET0   = IE^1;
sbit EX0   = IE^0;

/*  P3 (B0) */

sbit INT3  = P3^7;
sbit INT2  = P3^6;
sbit T1    = P3^5;
sbit TOCK0 = P3^4;
sbit T0    = P3^4;
sbit INT1  = P3^3;
sbit INT0  = P3^2;
sbit TXD   = P3^1;
sbit RXD   = P3^0;

sbit P3_7   = P3^7;
sbit P3_6   = P3^6;
sbit P3_5   = P3^5;
sbit P3_4   = P3^4;
sbit P3_3   = P3^3;
sbit P3_2   = P3^2;
sbit P3_1   = P3^1;
sbit P3_0   = P3^0;

/*  IP (B8H) */

sbit PX3   = IP^7;
sbit PX2    = IP^6;
sbit PT2   = IP^5;
sbit PS    = IP^4;
sbit PT1   = IP^3;
sbit PX1   = IP^2;
sbit PT0   = IP^1;
sbit PX0   = IP^0;

/*  PSW (D0H)*/  

sbit CY    = PSW^7;
sbit AC    = PSW^6;
sbit F0    = PSW^5;
sbit RS1   = PSW^4;
sbit RS0   = PSW^3;
sbit OV    = PSW^2;
sbit P     = PSW^0; //8052 only


/* Port 4 (E8H) */

sbit P4_3   = P4^3;
sbit P4_2   = P4^2;
sbit P4_1   = P4^1;
sbit P4_0   = P4^0;

/*  SICON (F8H) */

sbit CR2     = SICON^7;
sbit ENSI    = SICON^6;
sbit STA     = SICON^5;
sbit STO     = SICON^4;
sbit SI         = SICON^3;
sbit AA      = SICON^2;
sbit CR1     = SICON^1;
sbit CR0     = SICON^0;

/*  USB Special Function Registers   */
/*  The special function registers which are dedicated to the USB operation are grouped in 
  the external memory address space and share the addresses 0xFF00 to 0xFFFF with the 
  physical external data memory. That is, the user should use the instruction ¨MOVX @DPTR〃
  to access these USB SFRs */

/* Device Control Register           */
#define    DCON        0xC0	
/* USB Address Register              */
#define    UADDR       0xD8
/* USB Power Control Register        */
#define    UPCON       0xC9
/* Interrupt Enable Register         */
 #define    IEN         0xD9
/* USB Interrupt Enable Register     */
#define    UIE         0xDA
/* USB Interrupt Flag Register       */
#define    UIFLG       0xDB
/* USB Interrupt Enable Register 1   */
#define    UIE1        0xDC
/* USB Interrupt Flag Register 1     */
#define    UIFLG1      0xDD
/* Endpoint Index Register           */
#define    EPINDEX     0xF1
/* Endpoint Control Register         */
#define    EPCON       0xE1
/* Endpoint Receive Status Register  */
#define    RXSTAT      0xE2
/* Receive FIFO Data Register        */
#define    RXDAT       0xE3
/* Receive FIFO Control Register     */
#define    RXCON       0xE4
/* Receive FIFO Byte Count Register  */
#define    RXCNT       0xE6
/* Endpoint Transmit Status Register */
#define    TXSTAT      0xF2
/* Transmit FIFO Data Register       */
#define    TXDAT       0xF3
/* Transmit FIFO Control Register    */
#define    TXCON       0xF4
/* Transmit FIFO Byte Count Register */
#define    TXCNT       0xF6
/* Serial I/O Control Register       */
#define    SIOCTL      0xC2