init.c

adc 3208 上面实现图片旋转的实例

void InitRenderingEngine_zy()
{
	*(volatile unsigned short*)(0x300008c) = 0x0008; // Rendering engine control register
	*(volatile unsigned short*)(0x3000080) = 0x0000; // Command queue front pointer register
	*(volatile unsigned short*)(0x30000a6) = 0x0000; // Flip command count register
	
	// Rendering bank1 address select register
	// *(unsigned short*)(0x3000090) = 0x0000;   // backbuffer address: 04100000h
	*(volatile unsigned short*)(0x3000090) = 0x8000; // backbuffer address: 04400000h
	
	// Rendering engine control register
	// *(unsigned short*)(0x300008c) = 0x0004; // dither mode : 2x2,    render target : back-buffer
	// *(unsigned short*)(0x300008c) = 0x0005; // dither mode : 4x4,    render target : back-buffer
	// *(unsigned short*)(0x300008c) = 0x0006; // dither mode : disable,render target : back-buffer
	// *(unsigned short*)(0x300008c) = 0x0084; // dither mode : 2x2,    render target : front-buffer
	// *(unsigned short*)(0x300008c) = 0x0085; // dither mode : 4x4,    render target : front-buffer
	*(volatile unsigned short*)(0x300008c) = 0x0086; // dither mode : disable,render target : front-buffer
}

void PushCommand( void(*WritePacket)(volatile unsigned short *packet_addr) )
{
	volatile unsigned short reg_front = *(volatile unsigned short*)(0x3000080);
	unsigned short reg_rear;
	unsigned short next_front = (reg_front+1)%2048;
	volatile unsigned short *packet_addr = (volatile unsigned short*)(0x03800000 + ( 64 * (unsigned long)reg_front ));
	
	// make command packet
	WritePacket( packet_addr );
	
	// command queue啊 full捞扼搁 扁促赴促.
	while( 1 )
	{
	reg_rear = *(volatile unsigned short*)(0x3000082);
	if( next_front != reg_rear ) break;
	}
	
	// front pointer甫 刘啊矫挪促.
	*(volatile unsigned short*)(0x3000080) = next_front;
}

///////////////////////////////////////////////
// CRT setting
// 		for vid clock = 14.318Mhz
///////////////////////////////////////////////
void CRT_320x240_noninterlace()
{
	unsigned long ModeParam[11][13] = {
		// 640x480 interlace TV
		{ 0x0000, 0x0091, 0x6f3f, 0x027f, 0x0000, 0x3f00, 0x0011, 
			0x00e0, 0x0000, 0x0000, 0x003c, 0x0000, 0x2000 },			
		// 320x240 noninterlace TV
		{ 0x0000, 0x0093, 0x2121, 0x013f, 0x0000, 0x0000, 0x0013, 
			0x00ef, 0x05c6, 0x09f9, 0x0021, 0x0000, 0x4001 },
		// 360x240 noninterlace TV
		{ 0x0000, 0x0093, 0x2121, 0x0168, 0x0000, 0x0000, 0x0013, 
			0x00ef, 0x05c6, 0x09f9, 0x0021, 0x0000, 0x4001 },
	        //640x480 interlace TV
		{0x0000, 0x0088, 0x3c80, 639, 0x0000, 0x3809, 0x0011,
		(239),  0x0, 0x0,  0x003c, 0x0000, 0x2000},
	
		//640x480 noninterlace VGA monitor 25.175M
		{0x0000, 0x0091, 0x2D60, 646, 0x000D, 0x2609, 0x001E,
		(484),  ((0x01<<10)|399), ((0x01<<11)|1031),  0x0032, 0x0000, 0x4001},

		//800x512 noninterlace VGA monitor 43M
		{0x0000, 0x0091, 0x527f, 825, 0x0000, 0x0, 0x0a,
		(511),  ((0x01<<10)|525), ((0x01<<11)|1225),  50, 0x0000, 0x4001}, //505, 1240

		//800x512 noninterlace VGA monitor 32-40M
		{0x0000, 0x0091, 0x7656, 825, 0x0000, 0x0101, 14,
		(511),  ((0x01<<10)|485), ((0x01<<11)|1235),  50, 0x0000, 0x4001}, 
		//36M 485, 1235 OK,x_offset=30, H is small

		//800x512 noninterlace VGA monitor 32-40M
		{0x0000, 0x0091, 0x7050, 825, 0x0000, 0x0, 16,
		(511),  ((0x01<<10)|487), ((0x01<<11)|1235),  65, 0x0000, 0x4001}, 
		//0x7050,16,487,1235,65 at 36M OK,X_Offset=40 H is small

		//800x512 noninterlace VGA monitor 32-40M
		{0x0000, 0x0091, 0x7050, 830, 0x0000, 0x0, 16,
		(511),  ((0x01<<10)|486), ((0x01<<11)|1235),  65, 0x0000, 0x4001}, 
		//0x7050,16,486or487,1235,65 at 36M OK,X_Offset=40 H is little small

		//9:800x512 noninterlace VGA monitor 36M
		{0x0000, 0x0091, 0x2d80, 825, 0x25, 0x2613, 0x0a,
		(511),  ((0x01<<10)|525), ((0x01<<11)|1225),  50, 0x0000, 0x4001},
		//
		
        //720x480 interlace TV
		{0x0000, 0x0088, 0x3f3f, 720, 16, 0x2609, 0x0014,
		(239),  0x0, 0x0,  100, 0x0000, 0x2000}

		};

	long i;
	unsigned long *SelectedModeParam;
	volatile unsigned long *CRT_reg = (volatile unsigned long*)0x01803400;
	
	// select screen mode 360x240 noninterlace
	SelectedModeParam = ModeParam[3]; //VGA640*480:4,VGA800*511:8 forAMA, TV:3, TV10
	
	for( i=0; i<13; i++ )
	{
		if( i!=1 )
			CRT_reg[i] = SelectedModeParam[i];
	}
	CRT_reg[1] = SelectedModeParam[1];
}

///////////////////////////////////////////////
// memory controller reset
//		for FMEM, TMEM
///////////////////////////////////////////////
void VR0_memory_controller_reset()
{
	#define TMEM_TYPE	2	// TMem = 64MBit 4Banks
	#define FMEM_TYPE	2	// FMem = 64MBit 4banks
	#define MEM_TYPE	((TMEM_TYPE<<2)|FMEM_TYPE)
	*(volatile unsigned short*)(0x3000100) = (unsigned short)(0x8000|MEM_TYPE);
	*(volatile unsigned short*)(0x3000106) = 0x0af2;
	*(volatile unsigned short*)(0x3000108) = 0x0af2;
}


extern void start(); 
extern void TIMER1();
//extern void VSP();

typedef void (*fp)(void);

#define NOTUSEDISR     (fp)(0) 

const fp HardwareVector[] __attribute__((section (".vects")))= {
	    start    , /* V00 : Reset Vector             */
	    NOTUSEDISR, /* V01 : NMI Vector               */
	    NOTUSEDISR, /* V02 : Interrupt Auto Vector   */
	    NOTUSEDISR, /* V03 : Double Falule Exception */
	    NOTUSEDISR, /* V04 : Bus Error exception     */
	    NOTUSEDISR, /* V05 : Reserved                */
	    NOTUSEDISR, /* V06 : Reserved                */
	    NOTUSEDISR, /* V07 : Reserved                */
	    NOTUSEDISR, /* V08 : Co-processor Exception  */
	    NOTUSEDISR, /* V09 : Co-processor Exception  */
	    NOTUSEDISR, /* V0A : Co-processor Exception  */
	    NOTUSEDISR, /* V0B : Co-processor Exception  */
	    NOTUSEDISR, /* V0C : OSI Reset Vector        */
	    NOTUSEDISR, /* V0D : OSI break exception     */
	    NOTUSEDISR, /* V0E : Reserved                */
	    NOTUSEDISR, /* V0F : Reserved                */
	    NOTUSEDISR, /* V10 : SWI 00 Vector           */
	    NOTUSEDISR, /* V11 : SWI 01 Vector           */
	    NOTUSEDISR, /* V12 : SWI 02 Vector           */
	    NOTUSEDISR, /* V13 : SWI 03 Vector           */
	    NOTUSEDISR, /* V14 : SWI 04 Vector           */
	    NOTUSEDISR, /* V15 : SWI 05 Vector           */
	    NOTUSEDISR, /* V16 : SWI 06 Vector           */
	    NOTUSEDISR,	/* V17 : SWI 07 Vector           */
	    NOTUSEDISR, /* V18 : SWI 08 Vector           */
	    NOTUSEDISR, /* V19 : SWI 09 Vector           */
	    NOTUSEDISR, /* V1A : SWI 0A Vector           */
	    NOTUSEDISR, /* V1B : SWI 0B Vector           */
	    NOTUSEDISR, /* V1C : SWI 0C Vector           */
	    NOTUSEDISR, /* V1D : SWI 0D Vector           */
	    NOTUSEDISR, /* V1E : SWI 0E Vector           */
	    NOTUSEDISR, /* V1F : SWI 0F Vector           */

            NOTUSEDISR    , // V20 : User 00 Vector V20 : TIMER0          
         TIMER1,  // TIMER1        , // V21 : User 01 Vector V21 : TIMER1         
        NOTUSEDISR    , // V22 : User 02 Vector V22 : DPINT         
		NOTUSEDISR, /* V23 : PPM0					 */
		NOTUSEDISR, /* V24 : PPM1					 */
		NOTUSEDISR, /* V25 : EXT_IRQ0				 */
		NOTUSEDISR, /* V26 : EXT_IRQ1				 */
		NOTUSEDISR, /* V27 : DMA0					 */
		NOTUSEDISR, /* V28 : DMA1					 */
		NOTUSEDISR, /* V29 : TIMER2					 */
		NOTUSEDISR, /* V2A : TIMER3					 */
		NOTUSEDISR, /* V2B : EXT_IRQ2				 */
		NOTUSEDISR, /* V2C : EXT_IRQ3				 */
		NOTUSEDISR, /* V2D : UART0_RXE				 */
		NOTUSEDISR, /* V2E : UART0_RX				 */
		NOTUSEDISR, /* V2F : UART0_TX				 */
		NOTUSEDISR, /* V30 : UART1_RXE				 */
	    	NOTUSEDISR, /* V31 : UART1_RX				 */
		NOTUSEDISR, /* V32 : UART1_TX				 */
		NOTUSEDISR, /* V33 : EXT_IRQ4				 */
		NOTUSEDISR     , // V34 : User 14 Vector  V34 : EXT_IRQ5 */
		NOTUSEDISR, /* V35 : EXT_IRQ6				 */
		NOTUSEDISR, /* V36 : EXT_IRQ7				 */
		NOTUSEDISR, /* V37 : VEXT_SYNC				 */
		NOTUSEDISR, /* V38 : VSP					 */
		NOTUSEDISR, /* V39 : PPM_OVF				 */
		NOTUSEDISR, /* V3A : PWM					 */
	    NOTUSEDISR, /* V3B : User 1B Vector          */
	    NOTUSEDISR, /* V3C : User 1C Vector          */
	    NOTUSEDISR, /* V3D : User 1D Vector          */
	    NOTUSEDISR, /* V3E : User 1E Vector          */
	    NOTUSEDISR, /* V3F : User 1F Vector          */
	    NOTUSEDISR, /* V40 : User 20 Vector          */
	    NOTUSEDISR, /* V41 : User 21 Vector          */
	    NOTUSEDISR, /* V42 : User 22 Vector          */
	    NOTUSEDISR, /* V43 : User 23 Vector          */
	    NOTUSEDISR, /* V44 : User 24 Vector          */
	    NOTUSEDISR, /* V45 : User 25 Vector          */
	    NOTUSEDISR, /* V46 : User 26 Vector          */
	    NOTUSEDISR, /* V47 : User 27 Vector          */
	    NOTUSEDISR, /* V48 : User 28 Vector          */
	    NOTUSEDISR, /* V49 : User 29 Vector          */
	    NOTUSEDISR, /* V4A : User 2A Vector          */
	    NOTUSEDISR, /* V4B : User 2B Vector          */
	    NOTUSEDISR, /* V4C : User 2C Vector          */
	    NOTUSEDISR, /* V4D : User 2D Vector          */
	    NOTUSEDISR, /* V4E : User 2E Vector          */
	    NOTUSEDISR  /* V4F : User 2F Vector          */
};