📄 ceddk.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
Module Name:
cedddk.h
Abstract:
This module defines the NT types, constants, and functions that are
exposed to device drivers.
Revision History:
--*/
#ifndef _CEDDK_
#define _CEDDK_
#define NTKERNELAPI
#define NTHALAPI
#ifdef __cplusplus
extern "C" {
#endif
#define PAGE_SIZE UserKInfo[KINX_PAGESIZE]
// Warning : This assume only 1K & 4K pages available under CE. Else Break
#define PAGE_SHIFT ( (PAGE_SIZE == 0x1000) ? 12L : \
((PAGE_SIZE == 0x400) ? 10L : (DBGCHK("Invalid Page Size",1),0) ) )
//
// NTSTATUS
//
typedef LONG NTSTATUS, *PNTSTATUS;
//
// Status values are 32 bit values layed out as follows:
//
// 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +---+-+-------------------------+-------------------------------+
// |Sev|C| Facility | Code |
// +---+-+-------------------------+-------------------------------+
//
// where
//
// Sev - is the severity code
//
// 00 - Success
// 01 - Informational
// 10 - Warning
// 11 - Error
//
// C - is the Customer code flag
//
// Facility - is the facility code
//
// Code - is the facility's status code
//
//
// Generic test for success on any status value (non-negative numbers
// indicate success).
//
#define NT_SUCCESS(Status) ((NTSTATUS)(Status) >= 0)
//
// Generic test for information on any status value.
//
#define NT_INFORMATION(Status) ((ULONG)(Status) >> 30 == 1)
//
// Generic test for warning on any status value.
//
#define NT_WARNING(Status) ((ULONG)(Status) >> 30 == 2)
//
// Generic test for error on any status value.
//
#define NT_ERROR(Status) ((ULONG)(Status) >> 30 == 3)
#define APPLICATION_ERROR_MASK 0x20000000
#define ERROR_SEVERITY_SUCCESS 0x00000000
#define ERROR_SEVERITY_INFORMATIONAL 0x40000000
#define ERROR_SEVERITY_WARNING 0x80000000
#define ERROR_SEVERITY_ERROR 0xC0000000
typedef LARGE_INTEGER PHYSICAL_ADDRESS, *PPHYSICAL_ADDRESS; // windbgkd
typedef enum _INTERFACE_TYPE {
InterfaceTypeUndefined = -1,
Internal,
Isa,
Eisa,
MicroChannel,
TurboChannel,
PCIBus,
VMEBus,
NuBus,
PCMCIABus,
CBus,
MPIBus,
MPSABus,
ProcessorInternal,
InternalPowerBus,
PNPISABus,
PNPBus,
MaximumInterfaceType
} INTERFACE_TYPE, *PINTERFACE_TYPE;
//
// Define types of bus information.
//
typedef enum _BUS_DATA_TYPE {
ConfigurationSpaceUndefined = -1,
Cmos,
EisaConfiguration,
Pos,
CbusConfiguration,
PCIConfiguration,
VMEConfiguration,
NuBusConfiguration,
PCMCIAConfiguration,
MPIConfiguration,
MPSAConfiguration,
PNPISAConfiguration,
MaximumBusDataType
} BUS_DATA_TYPE, *PBUS_DATA_TYPE;
//
// A PCI driver can read the complete 256 bytes of configuration
// information for any PCI device by calling:
//
// ULONG
// HalGetBusData (
// IN BUS_DATA_TYPE PCIConfiguration,
// IN ULONG PciBusNumber,
// IN PCI_SLOT_NUMBER VirtualSlotNumber,
// IN PPCI_COMMON_CONFIG &PCIDeviceConfig,
// IN ULONG sizeof (PCIDeviceConfig)
// );
//
// A return value of 0 means that the specified PCI bus does not exist.
//
// A return value of 2, with a VendorID of PCI_INVALID_VENDORID means
// that the PCI bus does exist, but there is no device at the specified
// VirtualSlotNumber (PCI Device/Function number).
//
//
// begin_ntminiport begin_ntndis
typedef struct _PCI_SLOT_NUMBER {
union {
struct {
ULONG DeviceNumber:5;
ULONG FunctionNumber:3;
ULONG Reserved:24;
} bits;
ULONG AsULONG;
} u;
} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
#define PCI_TYPE0_ADDRESSES 6
#define PCI_TYPE1_ADDRESSES 2
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID; // (ro)
USHORT DeviceID; // (ro)
USHORT Command; // Device control
USHORT Status;
UCHAR RevisionID; // (ro)
UCHAR ProgIf; // (ro)
UCHAR SubClass; // (ro)
UCHAR BaseClass; // (ro)
UCHAR CacheLineSize; // (ro+)
UCHAR LatencyTimer; // (ro+)
UCHAR HeaderType; // (ro)
UCHAR BIST; // Built in self test
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine; //
UCHAR InterruptPin; // (ro)
UCHAR MinimumGrant; // (ro)
UCHAR MaximumLatency; // (ro)
} type0;
struct _PCI_HEADER_TYPE_1 {
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
UCHAR PrimaryBusNumber;
UCHAR SecondaryBusNumber;
UCHAR SubordinateBusNumber;
UCHAR SecondaryLatencyTimer;
UCHAR IOBase;
UCHAR IOLimit;
USHORT SecondaryStatus;
USHORT MemoryBase;
USHORT MemoryLimit;
USHORT PrefetchableMemoryBase;
USHORT PrefetchableMemoryLimit;
ULONG PrefetchableMemoryBaseUpper32;
ULONG PrefetchableMemoryLimitUpper32;
USHORT IOBaseUpper;
USHORT IOLimitUpper;
ULONG Reserved2;
ULONG ExpansionROMBase;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type1;
} u;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
#define PCI_MAX_BUS 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_INVALID_VENDORID 0xFFFF
//
// Bit encodings for PCI_COMMON_CONFIG.HeaderType
//
#define PCI_MULTIFUNCTION 0x80
#define PCI_DEVICE_TYPE 0x00
#define PCI_BRIDGE_TYPE 0x01
//
// Bit encodings for PCI_COMMON_CONFIG.Command
//
#define PCI_ENABLE_IO_SPACE 0x0001
#define PCI_ENABLE_MEMORY_SPACE 0x0002
#define PCI_ENABLE_BUS_MASTER 0x0004
#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
#define PCI_ENABLE_PARITY 0x0040 // (ro+)
#define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+)
#define PCI_ENABLE_SERR 0x0100 // (ro+)
#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro)
//
// Bit encodings for PCI_COMMON_CONFIG.Status
//
#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro)
#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
#define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide
#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
//
// Base Class Code encodings for Base Class (from PCI spec rev 2.1).
//
#define PCI_CLASS_PRE_20 0x00
#define PCI_CLASS_MASS_STORAGE_CTLR 0x01
#define PCI_CLASS_NETWORK_CTLR 0x02
#define PCI_CLASS_DISPLAY_CTLR 0x03
#define PCI_CLASS_MULTIMEDIA_DEV 0x04
#define PCI_CLASS_MEMORY_CTLR 0x05
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
#define PCI_CLASS_BASE_SYSTEM_DEV 0x08
#define PCI_CLASS_INPUT_DEV 0x09
#define PCI_CLASS_DOCKING_STATION 0x0a
#define PCI_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
// 0d thru fe reserved
#define PCI_CLASS_NOT_DEFINED 0xff
//
// Sub Class Code encodings (PCI rev 2.1).
//
// Class 00 - PCI_CLASS_PRE_20
#define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
#define PCI_SUBCLASS_PRE_20_VGA 0x01
// Class 01 - PCI_CLASS_MASS_STORAGE_CTLR
#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
#define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
#define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
#define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
#define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
#define PCI_SUBCLASS_MSC_OTHER 0x80
// Class 02 - PCI_CLASS_NETWORK_CTLR
#define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
#define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
#define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
#define PCI_SUBCLASS_NET_ATM_CTLR 0x03
#define PCI_SUBCLASS_NET_OTHER 0x80
// Class 03 - PCI_CLASS_DISPLAY_CTLR
// N.B. Sub Class 00 could be VGA or 8514 depending on Interface byte
#define PCI_SUBCLASS_VID_VGA_CTLR 0x00
#define PCI_SUBCLASS_VID_XGA_CTLR 0x01
#define PCI_SUBCLASS_VID_OTHER 0x80
// Class 04 - PCI_CLASS_MULTIMEDIA_DEV
#define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
#define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
#define PCI_SUBCLASS_MM_OTHER 0x80
// Class 05 - PCI_CLASS_MEMORY_CTLR
#define PCI_SUBCLASS_MEM_RAM 0x00
#define PCI_SUBCLASS_MEM_FLASH 0x01
#define PCI_SUBCLASS_MEM_OTHER 0x80
// Class 06 - PCI_CLASS_BRIDGE_DEV
#define PCI_SUBCLASS_BR_HOST 0x00
#define PCI_SUBCLASS_BR_ISA 0x01
#define PCI_SUBCLASS_BR_EISA 0x02
#define PCI_SUBCLASS_BR_MCA 0x03
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_SUBCLASS_BR_PCMCIA 0x05
#define PCI_SUBCLASS_BR_NUBUS 0x06
#define PCI_SUBCLASS_BR_CARDBUS 0x07
#define PCI_SUBCLASS_BR_OTHER 0x80
// Class 07 - PCI_CLASS_SIMPLE_COMMS_CTLR
// N.B. Sub Class 00 and 01 additional info in Interface byte
#define PCI_SUBCLASS_COM_SERIAL 0x00
#define PCI_SUBCLASS_COM_PARALLEL 0x01
#define PCI_SUBCLASS_COM_OTHER 0x80
// Class 08 - PCI_CLASS_BASE_SYSTEM_DEV
// N.B. See Interface byte for additional info.
#define PCI_SUBCLASS_SYS_INTERRUPT_CTLR 0x00
#define PCI_SUBCLASS_SYS_DMA_CTLR 0x01
#define PCI_SUBCLASS_SYS_SYSTEM_TIMER 0x02
#define PCI_SUBCLASS_SYS_REAL_TIME_CLOCK 0x03
#define PCI_SUBCLASS_SYS_OTHER 0x80
// Class 09 - PCI_CLASS_INPUT_DEV
#define PCI_SUBCLASS_INP_KEYBOARD 0x00
#define PCI_SUBCLASS_INP_DIGITIZER 0x01
#define PCI_SUBCLASS_INP_MOUSE 0x02
#define PCI_SUBCLASS_INP_OTHER 0x80
// Class 0a - PCI_CLASS_DOCKING_STATION
#define PCI_SUBCLASS_DOC_GENERIC 0x00
#define PCI_SUBCLASS_DOC_OTHER 0x80
// Class 0b - PCI_CLASS_PROCESSOR
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_COPROCESSOR 0x40
// Class 0c - PCI_CLASS_SERIAL_BUS_CTLR
#define PCI_SUBCLASS_SB_IEEE1394 0x00
#define PCI_SUBCLASS_SB_ACCESS 0x01
#define PCI_SUBCLASS_SB_SSA 0x02
#define PCI_SUBCLASS_SB_USB 0x03
#define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04
//
// Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses
//
#define PCI_ADDRESS_IO_SPACE 0x00000001 // (ro)
#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 // (ro)
#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 // (ro)
#define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
#define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
#define PCI_TYPE_32BIT 0
#define PCI_TYPE_20BIT 2
#define PCI_TYPE_64BIT 4
//
// Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses
//
#define PCI_ROMADDRESS_ENABLED 0x00000001
//
// ISA PnP Structures
//
typedef struct _ISA_PNP_LOGICAL_DEVICE_INFO
{
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