📄 txxinittable.lst
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130 0xE4 , 0x10,
131 0xE5 , 0xcd, // 0x55, Bruce, 2007/08/02
132 0xE6 , 0x2C,
133 0xE8 , 0x15,
134 0xE9 , 0x00,
135 0xEC , 0x40, //Enable SAR
136 0x34 , 0x11, //Enable SAR interrupt.
137 0x33 , 0xFF, //Disable All interrupt.
138 0x32 , 0xFF, //Clear All interrupt.
139 0xE2 , 0x11,
140 0xff , 0x00// End of register settings, bruce, 2006/01/09
141 };
142 REGADRVAL code stInitT10xP1[]={
143 ///adr , value
144 0x50 , 0x30,
145 0x51 , 0x11,
146 0xB8 , 0xC0,
147 0xD3 , 0x01,
148 0xDF , 0x00,
149 0xFF , 0x00 // End of register settings
150 };
151
152 REGADRVAL code stInitT10xP2[]={
153 //adr , value
154 0x3f , 0x00, //ADC_ROFF // Change by Sherman 06'01'10
155 0x24 , 0xe9, //0 //0x24
156 0x25 , 0x0F, //0x25
157 //Video Register Page Setted
158 0x2E , 0x82, //HACT_START_REG
159 0x2F , 0x30, //HACT_WIDTH_REG
160 0x3F , 0x00, //SOFT_RESET_REG
161 0xc0 , 0x14, //5 //0xc0
162 0xe0 , 0x10, //0xe0
163 0x0C , 0x8a, //CHROMA_AGC_REG
164 0x18 , 0x21, //CHROMA_DTO0_REG
165 0x19 , 0xf0, //CHROMA_DTO1_REG
166 0x1A , 0x7c, //10 //CHROMA_DTO2_REG
167 0x1B , 0x0f, //CHROMA_DTO3_REG
-
168 0x30 , 0x24, //VACT_START_REG
169 0x31 , 0x61, //VACT_HEIGHT_REG
170 0x82 , 0x42, //COMB_FILTERCFG_REG
171
172 0x04 , 0xD8, //15 //HAGC_REG // Change by Sherman for Gamma Adjustment 05'12'19
173 0x10 , 0x27, //AGC_PKNO_REG
174 0x00 , 0x00, //SRCSEL_COMBF_REG
175 0x03 , 0x00, //COMB_FILTERMODE_REG
C51 COMPILER V8.08 TXXINITTABLE 11/23/2007 00:57:18 PAGE 4
176 0x02 , 0x4B, //YC_AGC_REG
177 0x11 , 0xb9, //20 //AGC_PKGT_CTRL_REG
178
179 //Color
180 0x01 , 0x00,//(I1CReadByte(TW803_P0+4, 0x01)|0x01), //BW_CTRL_REG
181
182 0x80 , 0x05,//For char clear //LUMINANCE_PKCTRL_REG
183 0x07 , 0x01,//For color bar clear //YC_OPCTRL_REG
184 0x08 , 0x40, //CONTRAST_REG // Change by Sherman for G
-amma Adjustment 05'12'19
185 0x0A , 0x80, //25 //SAT_REG
186 0x09 , 0x6E, //BRIGHT_REG
187
188 0x2d , 0x48, // Add by Sherman 06'01'10s
189 0x3f , 0x01, //ADC_ROFF // Change by Sherman 06'01'10
190 0xff , 0x00, // End of register settings, bruce, 2006/01/09
191 };
192 REGADRVAL code stInitOUT_T[]={
193 #ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
200 0xC8 , DFDIV_40, //PLLDIV_F
201 0xC9 , DIDIV, //PLLDIV_I
202 #endif
203 //DSP Colck Polarity
204 0xC1 , 0xc8, //POUT_CTRL3_REG
205 //H&V Main Display Pixel Clock Setted
206 0xDC ,(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
207 0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
208 0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
209 0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
210 //H&V Display Pixel Clock Setted
211
212 #ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
217 0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
218 0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
219 0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
220 0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
221 0xB4 ,(H_Size&0xFF), //H Width //DWHSZ_L_REG
222 0xB5 ,(H_Size>>8), //DWHSZ_H_REG
223 0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
224 0xB7 ,(V_Size>>8), //DWVSZ_H_REG
225 0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
226 0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
227 0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
228 0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
229 0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
230 0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
231 0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
232 0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
233 0xff , 0x00// End of register settings, bruce, 2006/01/09
234
235 };
236 uCHAR code ucaSignalStdRegP2[6]={
C51 COMPILER V8.08 TXXINITTABLE 11/23/2007 00:57:18 PAGE 5
237 0x0c, 0x18, 0x19, 0x1a, 0x1b, 0x82
238 };
239 uCHAR code ucaSignalStdValP2[36]={
240 //NTSC
241 0x8a, 0x21, 0xf0, 0x7c, 0x0f, 0x42 ,
242 //NTSC 4
243 0x8a, 0x2a, 0x09, 0x8a, 0xcb, 0x42 ,
244 //PAL_M
245 0x67, 0x21, 0xe6, 0xef, 0xa3, 0x52 ,
246 //PAL
247 0x67, 0x2a, 0x09, 0x8a, 0xcb, 0x52 ,
248 //PAL_CN
249 0x67, 0x21, 0xf6, 0x94, 0x46, 0x52 ,
250 //SECAM
251 0x80, 0x28, 0xb3, 0x3b, 0xb2, 0x52
252 };
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = 326 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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