📄 txxinittable.lst
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C51 COMPILER V8.08 TXXINITTABLE 11/23/2007 00:57:18 PAGE 1
C51 COMPILER V8.08, COMPILATION OF MODULE TXXINITTABLE
OBJECT MODULE PLACED IN .\Object\TxxInitTable.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE SourceFile\TxxInitTable.c LARGE BROWSE INCDIR(.\IncludeFile;.\IncludeFile\P
-anel;.\IncludeFile\Font_Icon) DEFINE(T108) DEBUG OBJECTEXTEND PRINT(.\List\TxxInitTable.lst) OBJECT(.\Object\TxxInitTabl
-e.obj)
line level source
1 #include "TxxInitTable.h"
2 #include "Common.h"
3 #include "System.h"
4 #include "Resolution.h"
5 #include "TWICreg.h"
6 //#define _Myson8957_
7 #include "Myson8957.h"
8 /****************************************************************************
9 * T10x Register No. and values for System and Tcon initial *
10 ****************************************************************************/
11 //====== InitT10x Register No. and values
12 REGADRVAL code stInitT10xP0[]={
13 //adr , value
14 0x0A , 0x60, //ADC_ROFF // Change by Sherman 06'01'10
15 0x0B , 0x60, //ADC_GOFF // Change by Sherman 06'01'10
16 0x0C , 0x60, //ADC_BOFF // Change by Sherman 06'01'10
17 0x16 , 0xD3,
18 0x1A , 0x87, //ADC_AGC_SEL_REG
19 0xC2 , 0x12, //POUT_VSYNC_CTRL_REG
20 //for image quality
21 0x6C , 0x80, //OP_SAT_REG
22 0x60 , 0x00, //DCTI_BW_REG
23 0x61 , 0x88,//For char clear //LUMA_PKCTRL_REG
24 0x62 , 0x18,//For char clear //BP_PKCOEF_REG
25 0x63 , 0x0F,//For char clear //HP_PKCOEF_REG
26 0x64 , 0x04,//For char clear //60 //LP_PKCOEF_REG
27 0x66 , 0x88,//For color clear enable DCTI //DCTI_GAINCO_REG
28 0X1C , 0xF0, //BLANK_SYNCLV_REG
29
30 0x97 , 0x95, //CSC_YCOEF_REG
31 0x98 , 0xCC, //CSC_CrRCOEF_REG
32 0x0D , 0x28, //5 //ADC_GENCTRL_REG
33 0xE0 , 0xa9,//92, //PW_MGRCTRL_REG
34 0x11 , 0x05, //YPbPr_CLPCTRL_REG
35 0x17 , 0x4c, // kenny 20060627
36 //Source Select--S Video
37 0x18 , 0x00, //ASRC_MUX_REG
38 0x19 , 0x07, //YCbCr_SW_REG
39 //DSP Clock
40 #ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
47 0xC8 , DFDIV_40, //PLLDIV_F
48 0xC9 , DIDIV, //PLLDIV_I
49 0xCA , DODIV, //PLLDIV_O
50 #endif
51 0xC0 , 0x81,
52 //DSP Colck Polarity
53 0xC1 , 0xc8, //POUT_CTRL3_REG
C51 COMPILER V8.08 TXXINITTABLE 11/23/2007 00:57:18 PAGE 2
54 //H&V Main Display Pixel Clock Setted
55 0xDC ,(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
56 0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
57 0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
58 0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
59 //H&V Display Pixel Clock Setted
60
61 #ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
66 0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
67 0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
68 0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
69 0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
70 0xB4 ,(H_Size&0xFF), //H Width //DWHSZ_L_REG
71 0xB5 ,(H_Size>>8), //DWHSZ_H_REG
72 0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
73 0xB7 ,(V_Size>>8), //DWVSZ_H_REG
74 0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
75 0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
76 0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
77 0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
78 0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
79 0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
80 0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
81 0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
82 //Scaling
83 0x72 , 0x33, //H Scale //SC_HOR_H1
84 0x73 , 0x73, //SC_HOR_H2
85 0x74 , 0x00, //V Scale //40 //SC_VER_V1
86 0x75 , 0x40, //SC_VER_V2
87 //LineBuffer Prefill
88 0xe2 , 0x11,
89 0x84 , 0x00, //LINE_BUF_L_REG
90 0x85 , 0x10, //LINE_BUF_H_REG
91 0xE1 , 0xa0, //OPIN_CFG_REG
92 0x50 , 0x10, //45 //VSYNC_TIME_MEA_REG
93 0x37 , 0x40, //VSYNC_MISSCNT_REG
94 0x38 , 0x50, //HSYNC_MISSCNT_L_REG
95 0x39 , 0x10, //HSYNC_MISSCNT_H_REG
96 0x3A , 0x20, //VSYNC_DLT_REG
97 0x3B , 0x03, //HSYNC_DLT_REG
98
99 #ifdef TCON
100 0xE0 , (0x91 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG, Bruce, 2006/01/09 for flexibility
-
101 0xE1 , 0xf4, //OPIN_CFG_REG
102 #else
0xE0 , (0x90 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG
0xE1 , 0x00, //OPIN_CFG_REG
#endif
106 0x9C , 0x02, //DITHERING
107 0x90 , 0x00, //IMG_FUNCTRL_REG
108 //De-Interlace enable
109 0x30 , 0x00,//(I1CReadByte(TW803_P0, 0x30)|0x01)//DITLC_VSHDW_REG
110 #ifdef OUT_PIN_CONF
0xE1 , OUT_PIN_CONF, //OPIN_CFG_REG
#endif
113
114 #ifdef Enable_HelfSample
C51 COMPILER V8.08 TXXINITTABLE 11/23/2007 00:57:18 PAGE 3
0x79 , 0x20,
#endif
117 #ifdef EnableDither
0x90 , ENCSC | ENDITHER,
0x9c , OutputBit,
#else
121 0x90 , ENCSC,
122 #endif
123 0xE0 , 0xB9,
124 0xE1 , 0xF4,
125 /* 0xE3 , 0x00, For T108/T128L
126 0xE5 , 0x55,
127 0xE7 , 0xB8,
128 0xE6 , 0x28,*/
129 0xE3 , 0x10,
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