mxarm11_sim.h

freescale i.mx31 BSP CE5.0全部源码

//------------------------------------------------------------------------------
//
//  Copyright (C) 2004,	Motorola Inc. All Rights Reserved
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//  Header: zeus_sim.h
//
//  Provides definitions for SIM module based on Freescale ARM11 chassis.
//
//------------------------------------------------------------------------------

#ifndef __ZEUS_SIM_H__
#define __ZEUS_SIM_H__

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct {
    REG32 PORT1_CNTL;               // 0x00: Port1 control register
    REG32 SETUP;                         // 0x04: Setup register
    REG32 PORT1_DETECT;          // 0x08: Port1 detect register
    REG32 PORT1_XMT_BUF;         // 0x0C: Port1 transmit buffer register
    REG32 PORT1_RCV_BUF;         // 0x10: Port1 receiver buffer register
    REG32 PORT0_CNTL;                // 0x14: Port0 control register
    REG32 CNTL;                              // 0x18: SIM control register
    REG32 CLOCK_SELECT;              // 0x1C: Clock select register
    REG32 RCV_THRESHOLD;         // 0x20: Receiver threshold register
    REG32 ENABLE;                        // 0x24: Enable register
    REG32 XMT_STATUS;                // 0x28: Transmit status register
    REG32 RCV_STATUS;                // 0x2C: Receiver status register
    REG32 INT_MASK;                      // 0x30: Interrupt mask register
    REG32 PORT0_XMT_BUF;          // 0x34: Port0 transmit buffer register
    REG32 PORT0_RCV_BUF;         // 0x38: Port0 receiver buffer register
    REG32 PORT0_DETECT;              // 0x3C: Port0 detect register
    REG32 DATA_FORMAT;               // 0x40: Data format register
    REG32 XMT_THRESHOLD;         // 0x44: Transmit threshold register
    REG32 GUARD_CNTL;                // 0x48: Transmit guard control register
    REG32 OD_CONFIG;                 // 0x4C: Open drain configuration register
    REG32 RESET_CNTL;                // 0x50: Reset control register
    REG32 CHAR_WAIT;                 // 0x54: Character wait time register
    REG32 GPCNT;                         // 0x58: General purpose counter register
    REG32 DIVISOR;                       // 0x5C: Divisor register
    REG32 BWT;                               // 0x60: Block wait time register
    REG32 BGT;                               // 0x64: Block guard time register 
    REG32 BWT_H;                         // 0x68: Block wait time register HIGH     
    } CSP_SIM_REG, *PCSP_SIM_REG;


//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define SIM_PORT1_CNTL_SAPD_LSH             0
#define SIM_PORT1_CNTL_SVEN_LSH             1
#define SIM_PORT1_CNTL_STEN_LSH             2
#define SIM_PORT1_CNTL_SRST_LSH             3
#define SIM_PORT1_CNTL_SCEN_LSH             4
#define SIM_PORT1_CNTL_SCSP_LSH             5
#define SIM_PORT1_CNTL_3VOLT_LSH                6
#define SIM_PORT1_CNTL_SFPD_LSH             7

#define SIM_SETUP_AMODE_LSH             0
#define SIM_SETUP_SPS_LSH               1

#define SIM_PORT1_DETECT_SDIM_LSH                0
#define SIM_PORT1_DETECT_SDI_LSH                1
#define SIM_PORT1_DETECT_SPDP_LSH                2
#define SIM_PORT1_DETECT_SPDS_LSH               3

#define SIM_PORT1_XMT_BUF_XMT_BUF_LSH               0

#define SIM_PORT1_RCV_BUF_RCV_BUF_LSH               0
#define SIM_PORT1_RCV_BUF_PE_LSH                8
#define SIM_PORT1_RCV_BUF_FE_LSH                9
#define SIM_PORT1_RCV_BUF_CWT_LSH               10

#define SIM_PORT0_CNTL_SAPD_LSH             0
#define SIM_PORT0_CNTL_SVEN_LSH             1
#define SIM_PORT0_CNTL_STEN_LSH             2
#define SIM_PORT0_CNTL_SRST_LSH             3
#define SIM_PORT0_CNTL_SCEN_LSH             4
#define SIM_PORT0_CNTL_SCSP_LSH             5
#define SIM_PORT0_CNTL_3VOLT_LSH                6
#define SIM_PORT0_CNTL_SFPD_LSH             7

#define SIM_CNTL_ICM_LSH                1
#define SIM_CNTL_ANACK_LSH	                2
#define SIM_CNTL_ONACK_LSH	                3
#define SIM_CNTL_SAMPLE12_LSH               4
#define SIM_CNTL_BAUD_SEL_LSH               6
#define SIM_CNTL_GPCNT_CLK_SEL_LSH              9
#define SIM_CNTL_CWTEN_LSH              11
#define SIM_CNTL_LRCEN_LSH              12
#define SIM_CNTL_CRCEN_LSH              13
#define SIM_CNTL_XMT_CRC_LRC_LSH                14
#define SIM_CNTL_BWTEN_LSH              15

#define SIM_CLOCK_SELECT_LSH                0

#define SIM_RCV_THRESHOLD_RDT_LSH               0
#define SIM_RCV_THRESHOLD_RTH_LSH               5

#define SIM_ENABLE_RCVEN_LSH                0
#define SIM_ENABLE_XMTEN_LSH                1

#define SIM_XMT_STATUS_XTE_LSH              0
#define SIM_XMT_STATUS_TFE_LSH              3
#define SIM_XMT_STATUS_ETC_LSH              4
#define SIM_XMT_STATUS_TC_LSH               5
#define SIM_XMT_STATUS_TFO_LSH              6
#define SIM_XMT_STATUS_TDTF_LSH             7
#define SIM_XMT_STATUS_GPCNT_LSH                8

#define SIM_RCV_STATUS_OEF_LSH              0
#define SIM_RCV_STATUS_RFD_LSH              4
#define SIM_RCV_STATUS_RDRF_LSH             5
#define SIM_RCV_STATUS_LRCOK_LSH                6
#define SIM_RCV_STATUS_CRCOK_LSH                7
#define SIM_RCV_STATUS_CWT_LSH              8
#define SIM_RCV_STATUS_RTE_LSH              9
#define SIM_RCV_STATUS_BWT_LSH              10
#define SIM_RCV_STATUS_BGT_LSH              11


#define SIM_INT_MASK_RIM_LSH                0
#define SIM_INT_MASK_TCIM_LSH               1
#define SIM_INT_MASK_OIM_LSH                2
#define SIM_INT_MASK_ETCIM_LSH              3
#define SIM_INT_MASK_TFEIM_LSH              4
#define SIM_INT_MASK_XMT_LSH                5
#define SIM_INT_MASK_TFOM_LSH               6
#define SIM_INT_MASK_TDTFM_LSH              7
#define SIM_INT_MASK_CPCNTM_LSH             8
#define SIM_INT_MASK_CWTM_LSH               9
#define SIM_INT_MASK_RTM_LSH                10
#define SIM_INT_MASK_BWTM_LSH               11
#define SIM_INT_MASK_BGTM_LSH               12

#define SIM_PORT0_XMT_BUF_XMT_BUF_LSH               0

#define SIM_PORT0_RCV_BUF_RCV_BUF_LSH               0
#define SIM_PORT0_RCV_BUF_PE_LSH                8
#define SIM_PORT0_RCV_BUF_FE_LSH                9
#define SIM_PORT0_RCV_BUF_CWT_LSH               10

#define SIM_PORT0_DETECT_SDIM_LSH               0
#define SIM_PORT0_DETECT_SDI_LSH                1
#define SIM_PORT0_DETECT_SPDP_LSH	                2
#define SIM_PORT0_DETECT_SPDS_LSH	                3

#define SIM_DATA_FORMAT_IC_LSH              0

#define SIM_XMT_THRESHOLD_TDT_LSH               0
#define SIM_XMT_THRESHOLD_XTH_LSH               4

#define SIM_GUARD_CNTL_GETU_LSH             0
#define SIM_GUARD_CNTL_RCVR11_LSH               8

#define SIM_OD_CONFIG_OD_P0_LSH             0
#define SIM_OD_CONFIG_OD_P1_LSH             1

#define SIM_RESET_CNTL_FLUSH_RCV_LSH                0
#define SIM_RESET_CNTL_FLUSH_XMT_LSH                1
#define SIM_RESET_CNTL_SOFT_RESET_LSH               2
#define SIM_RESET_CNTL_KILL_CLK_LSH             3
#define SIM_RESET_CNTL_DOZE_LSH             
#define SIM_RESET_CNTL_STOP_LSH             5
#define SIM_RESET_CNTL_DEBUG_LSH                6

#define SIM_CHAR_WAIT_CWT_LSH               0

#define SIM_GPCNT_LSH               0

#define SIM_DIVISOR_LSH                0

#define SIM_BWT_LSH             0

#define SIM_BGT_LSH             0

#define SIM_BWT_H_LSH               0

//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define SIM_PORT1_CNTL_SAPD_WID             1
#define SIM_PORT1_CNTL_SVEN_WID             1
#define SIM_PORT1_CNTL_STEN_WID             1
#define SIM_PORT1_CNTL_SRST_WID             1
#define SIM_PORT1_CNTL_SCEN_WID             1
#define SIM_PORT1_CNTL_SCSP_WID             1
#define SIM_PORT1_CNTL_3VOLT_WID                1
#define SIM_PORT1_CNTL_SFPD_WID         1

#define SIM_SETUP_AMODE_WID             1
#define SIM_SETUP_SPS_WID               1

#define SIM_PORT1_DETECT_SDIM_WID               1
#define SIM_PORT1_DETECT_SDI_WID                1
#define SIM_PORT1_DETECT_SPDP_WID               1
#define SIM_PORT1_DETECT_SPDS_WID               1

#define SIM_PORT1_XMT_BUF_XMT_BUF_WID               8

#define SIM_PORT1_RCV_BUF_RCV_BUF_WID               8
#define SIM_PORT1_RCV_BUF_PE_WID                1
#define SIM_PORT1_RCV_BUF_FE_WID                1
#define SIM_PORT1_RCV_BUF_CWT_WID               1

#define SIM_PORT0_CNTL_SAPD_WID             1
#define SIM_PORT0_CNTL_SVEN_WID             1
#define SIM_PORT0_CNTL_STEN_WID             1
#define SIM_PORT0_CNTL_SRST_WID             1
#define SIM_PORT0_CNTL_SCEN_WID             1
#define SIM_PORT0_CNTL_SCSP_WID             1
#define SIM_PORT0_CNTL_3VOLT_WID                1
#define SIM_PORT0_CNTL_SFPD_WID             1

#define SIM_CNTL_ICM_WID                1
#define SIM_CNTL_ANACK_WID              1
#define SIM_CNTL_ONACK_WID              1
#define SIM_CNTL_SAMPLE12_WID               1
#define SIM_CNTL_BAUD_SEL_WID               3
#define SIM_CNTL_GPCNT_CLK_SEL_WID              2
#define SIM_CNTL_CWTEN_WID              1
#define SIM_CNTL_LRCEN_WID              1
#define SIM_CNTL_CRCEN_WID              1
#define SIM_CNTL_XMT_CRC_LRC_WID                1
#define SIM_CNTL_BWTEN_WID              1

#define SIM_CLOCK_SELECT_WID                4

#define SIM_RCV_THRESHOLD_RDT_WID               5
#define SIM_RCV_THRESHOLD_RTH_WID               4

#define SIM_ENABLE_RCVEN_WID                1
#define SIM_ENABLE_XMTEN_WID                1

#define SIM_XMT_STATUS_XTE_WID              1
#define SIM_XMT_STATUS_TFE_WID              1
#define SIM_XMT_STATUS_ETC_WID              1
#define SIM_XMT_STATUS_TC_WID               1
#define SIM_XMT_STATUS_TFO_WID              1
#define SIM_XMT_STATUS_TDTF_WID             1
#define SIM_XMT_STATUS_GPCNT_WID                1

#define SIM_RCV_STATUS_OEF_WID              1
#define SIM_RCV_STATUS_RFD_WID              1
#define SIM_RCV_STATUS_RDRF_WID             1
#define SIM_RCV_STATUS_LRCOK_WID                1
#define SIM_RCV_STATUS_CRCOK_WID                1
#define SIM_RCV_STATUS_CWT_WID              1
#define SIM_RCV_STATUS_RTE_WID              1
#define SIM_RCV_STATUS_BWT_WID              1
#define SIM_RCV_STATUS_BGT_WID              1