mxarm11_ipu.h

freescale i.mx31 BSP CE5.0全部源码

#define IPU_IPU_INT_CTRL_1_DMAPF_4_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_5_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_6_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_7_EOF_EN_WID   1


// IPU CSI Registers
#define IPU_CSI_SENS_CONF_VSYNC_POL_WID         1
#define IPU_CSI_SENS_CONF_HSYNC_POL_WID         1
#define IPU_CSI_SENS_CONF_DATA_POL_WID          1
#define IPU_CSI_SENS_CONF_DISP_PIX_CLK_POL_WID  1
#define IPU_CSI_SENS_CONF_SENS_PRTCL_WID        3
#define IPU_CSI_SENS_CONF_SENS_CLK_SRC_WID      1
#define IPU_CSI_SENS_CONF_SENS_DATA_FORMAT_WID  2
#define IPU_CSI_SENS_CONF_DATA_WIDTH_WID        2
#define IPU_CSI_SENS_CONF_EXT_VSYNC_WID         1
#define IPU_CSI_SENS_CONF_DIV_RATIO_WID         8
#define IPU_CSI_SENS_CONF_MCLK_PIXCLK_RATIO_WID 4

#define IPU_CSI_SENS_FRM_SIZE_SENS_FRM_WIDTH_WID  12
#define IPU_CSI_SENS_FRM_SIZE_SENS_FRM_HEIGHT_WID 12

#define IPU_CSI_ACT_FRM_SIZE_ACT_FRM_WIDTH_WID  12
#define IPU_CSI_ACT_FRM_SIZE_ACT_FRM_HEIGHT_WID 12

#define IPU_CSI_OUT_FRM_CTRL_VSC_WID            8
#define IPU_CSI_OUT_FRM_CTRL_HSC_WID            8
#define IPU_CSI_OUT_FRM_CTRL_SKIP_ENC_WID       5
#define IPU_CSI_OUT_FRM_CTRL_SKIP_VF_WID        5
#define IPU_CSI_OUT_FRM_CTRL_IC_TV_MODE_WID     1
#define IPU_CSI_OUT_FRM_CTRL_VERT_DWNS_WID      1
#define IPU_CSI_OUT_FRM_CTRL_HORZ_DWNS_WID      1

#define IPU_CSI_TST_CTRL_PG_R_VALUE_WID         8
#define IPU_CSI_TST_CTRL_PG_G_VALUE_WID         8
#define IPU_CSI_TST_CTRL_PG_B_VALUE_WID         8
#define IPU_CSI_TST_CTRL_TEST_GEN_MODE_WID      1

#define IPU_CSI_CCIR_CODE_1_END_FLD0_BLNK_1ST_WID   3
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_BLNK_1ST_WID  3
#define IPU_CSI_CCIR_CODE_1_END_FLD0_BLNK_2ND_WID   3
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_BLNK_2ND_WID  3
#define IPU_CSI_CCIR_CODE_1_END_FLD0_ACTV_WID       3
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_ACTV_WID      3
#define IPU_CSI_CCIR_CODE_1_CCIR_ERR_DET_EN_WID     1

#define IPU_CSI_CCIR_CODE_2_END_FLD1_BLNK_1ST_WID   3
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_BLNK_1ST_WID  3
#define IPU_CSI_CCIR_CODE_2_END_FLD1_BLNK_2ND_WID   3
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_BLNK_2ND_WID  3
#define IPU_CSI_CCIR_CODE_2_END_FLD1_ACTV_WID       3
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_ACTV_WID      3

#define IPU_CSI_CCIR_CODE_3_CCIR_PRECOM_WID         24

#define IPU_CSI_FLASH_STROBE_1_CLOCK_SEL_WID           1
#define IPU_CSI_FLASH_STROBE_1_SENSE_ROW_DURATION_WID  16

#define IPU_CSI_FLASH_STROBE_2_STROBE_EN_WID           1
#define IPU_CSI_FLASH_STROBE_2_STROBE_POL_WID          1
#define IPU_CSI_FLASH_STROBE_2_STROBE_START_TIME_WID   13
#define IPU_CSI_FLASH_STROBE_2_STROBE_DURATION_WID     16


// IPU IC Registers
#define IPU_IC_CONF_PRPENC_EN_WID               1
#define IPU_IC_CONF_PRPENC_CSC1_WID             1
#define IPU_IC_CONF_PRPENC_ROT_EN_WID           1
#define IPU_IC_CONF_PRPVF_EN_WID                1
#define IPU_IC_CONF_PRPVF_CSC1_WID              1
#define IPU_IC_CONF_PRPVF_CSC2_WID              1
#define IPU_IC_CONF_PRPVF_CMB_WID               1
#define IPU_IC_CONF_PRPVF_ROT_EN_WID            1
#define IPU_IC_CONF_PP_EN_WID                   1
#define IPU_IC_CONF_PP_CSC1_WID                 1
#define IPU_IC_CONF_PP_CSC2_WID                 1
#define IPU_IC_CONF_PP_CMB_WID                  1
#define IPU_IC_CONF_PP_ROT_EN_WID               1
#define IPU_IC_CONF_IC_GLB_LOC_A_WID            1
#define IPU_IC_CONF_IC_KEY_COLOR_EN_WID         1
#define IPU_IC_CONF_RWS_EN_WID                  1
#define IPU_IC_CONF_CSI_MEM_WR_EN_WID           1

#define IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H_WID    14
#define IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H_WID    2
#define IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V_WID    14
#define IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V_WID    2

#define IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H_WID      14
#define IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H_WID      2
#define IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V_WID      14
#define IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V_WID      2

#define IPU_IC_PP_RSC_PP_RS_R_H_WID             14
#define IPU_IC_PP_RSC_PP_DS_R_H_WID             2
#define IPU_IC_PP_RSC_PP_RS_R_V_WID             14
#define IPU_IC_PP_RSC_PP_DS_R_V_WID             2

#define IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V_WID      8
#define IPU_IC_CMBP_1_IC_PP_ALPHA_V_WID         8

#define IPU_IC_CMBP_2_IC_KEY_COLOR_B_WID        8
#define IPU_IC_CMBP_2_IC_KEY_COLOR_G_WID        8
#define IPU_IC_CMBP_2_IC_KEY_COLOR_R_WID        8


// PF_CONF
#define IPU_PF_CONF_PF_TYPE_WID                 3
#define IPU_PF_CONF_H264_Y_PAUSE_EN_WID         1
#define IPU_PF_CONF_H264_Y_PAUSE_ROW_WID        6


// IDMAC_CONF
#define IPU_IDMAC_CONF_PRYM_WID                 2
#define IPU_IDMAC_CONF_SRCNT_WID                3
#define IPU_IDMAC_CONF_SINGLE_AHB_M_EN_WID      1


// SDC_COM_CONF
#define IPU_SDC_COM_CONF_SDC_MODE_WID           2
#define IPU_SDC_COM_CONF_BG_MCP_FROM_WID        1
#define IPU_SDC_COM_CONF_FG_MCP_FROM_WID        1
#define IPU_SDC_COM_CONF_FG_EN_WID              1
#define IPU_SDC_COM_CONF_GWSEL_WID              1
#define IPU_SDC_COM_CONF_SDC_GLB_LOC_A_WID      1
#define IPU_SDC_COM_CONF_SDC_KEY_COLOR_EN_WID   1
#define IPU_SDC_COM_CONF_MASK_EN_WID            1
#define IPU_SDC_COM_CONF_BG_EN_WID              1
#define IPU_SDC_COM_CONF_SHARP_WID              1
#define IPU_SDC_COM_CONF_DUAL_MODE_WID          1
#define IPU_SDC_COM_CONF_COC_WID                3

// SDC_GRAPH_WIND_CTRL
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_B_WID    8
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_G_WID    8
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_R_WID    8
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_ALPHA_V_WID        8

// SDC_FG_POS
#define IPU_SDC_FG_POS_FGYP_WID                    10
#define IPU_SDC_FG_POS_FGXP_WID                    10

// SDC_BG_POS
#define IPU_SDC_BG_POS_BGYP_WID                    10
#define IPU_SDC_BG_POS_BGXP_WID                    10

// SDC_CUR_POS
#define IPU_SDC_CUR_POS_CYP_WID                    10
#define IPU_SDC_CUR_POS_CYH_WID                    5
#define IPU_SDC_CUR_POS_CXP_WID                    10
#define IPU_SDC_CUR_POS_CXW_WID                    5

// SDC_CUR_BLINK_PWM_CTRL
#define IPU_SDC_CUR_BLINK_PWM_CTRL_BKDIV_WID    8
#define IPU_SDC_CUR_BLINK_PWM_CTRL_PWM_WID      8
#define IPU_SDC_CUR_BLINK_PWM_CTRL_BK_EN_WID    1
#define IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN_WID    1
#define IPU_SDC_CUR_BLINK_PWM_CTRL_SCR_WID      2

// SDC_CUR_MAP
#define IPU_SDC_CUR_MAP_CUR_COL_B_WID           8
#define IPU_SDC_CUR_MAP_CUR_COL_G_WID           8
#define IPU_SDC_CUR_MAP_CUR_COL_R_WID           8

// SDC_HOR_CONF
#define IPU_SDC_HOR_CONF_SCREEN_WIDTH_WID       10
#define IPU_SDC_HOR_CONF_H_SYNC_WIDTH_WID       6

// SDC_VER_CONF
#define IPU_SDC_VER_CONF_V_SYNC_WIDTH_L_WID     1
#define IPU_SDC_VER_CONF_SCREEN_HEIGHT_WID      10
#define IPU_SDC_VER_CONF_V_SYNC_WIDTH_WID       6

// SDC_SHARP_CONF_1
#define IPU_SDC_SHARP_CONF_1_CLS_RISE_DELAY_WID     8
#define IPU_SDC_SHARP_CONF_1_PS_FALL_DELAY_WID      8
#define IPU_SDC_SHARP_CONF_1_REV_TOGGLE_DELAY_WID   10

// SDC_SHARP_CONF_2
#define IPU_SDC_SHARP_CONF_2_CLS_FALL_DELAY_WID 10
#define IPU_SDC_SHARP_CONF_2_PS_RISE_DELAY_WID  10

// ADC_CONF
#define IPU_ADC_CONF_PRP_CHAN_EN_WID            1
#define IPU_ADC_CONF_PP_CHAN_EN_WID             1
#define IPU_ADC_CONF_MCU_CHAN_EN_WID            1
#define IPU_ADC_CONF_PRP_DISP_NUM_WID           2
#define IPU_ADC_CONF_PRP_ADDR_INC_WID           2
#define IPU_ADC_CONF_PRP_DATA_MAP_WID           1
#define IPU_ADC_CONF_PP_DISP_NUM_WID            2
#define IPU_ADC_CONF_PP_ADDR_INC_WID            2
#define IPU_ADC_CONF_PP_DATA_MAP_WID            1
#define IPU_ADC_CONF_PP_NO_TEARING_WID          1
#define IPU_ADC_CONF_SYS1_NO_TEARING_WID        1
#define IPU_ADC_CONF_SYS2_NO_TEARING_WID        1
#define IPU_ADC_CONF_SYS1_MODE_WID              3
#define IPU_ADC_CONF_SYS1_DISP_NUM_WID          2
#define IPU_ADC_CONF_SYS1_ADDR_INC_WID          2
#define IPU_ADC_CONF_SYS1_DATA_MAP_WID          1
#define IPU_ADC_CONF_SYS2_MODE_WID              2
#define IPU_ADC_CONF_SYS2_DISP_NUM_WID          2
#define IPU_ADC_CONF_SYS2_ADDR_INC_WID          2
#define IPU_ADC_CONF_SYS2_DATA_MAP_WID          1

// DI_HSP_CLK_PER
#define IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_1_WID 7
#define IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_2_WID 7

// DI_DISP0_TIME_CONF_1
#define IPU_DISP0_TIME_CONF_1_DISP0_IF_CLK_PER_WR_WID   12
#define IPU_DISP0_TIME_CONF_1_DISP0_IF_CLK_UP_WR_WID    10
#define IPU_DISP0_TIME_CONF_1_DISP0_IF_CLK_DOWN_WR_WID  10

// DI_DISP0_TIME_CONF_2
#define IPU_DISP0_TIME_CONF_2_DISP0_IF_CLK_PER_RD_WID   12
#define IPU_DISP0_TIME_CONF_2_DISP0_IF_CLK_UP_RD_WID    10
#define IPU_DISP0_TIME_CONF_2_DISP0_IF_CLK_DOWN_RD_WID  10

// DI_DISP0_TIME_CONF_3
#define IPU_DISP0_TIME_CONF_3_DISP0_PIX_CLK_PER_WID   12
#define IPU_DISP0_TIME_CONF_3_DISP0_READ_EN_WID       10
#define IPU_DISP0_TIME_CONF_3_DISP0_RD_WAIT_ST_WID    2


// DI_DISP3_TIME_CONF
#define IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR_WID  12
#define IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR_WID   10
#define IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR_WID 10



//ADC_SYSCHA1_SA
//ADC_SYSCHA2_SA
//ADC_PRPCHAN_SA
//ADC_PPCHAN_SA
#define IPU_ADC_CHA_CHAN_SA_WID                 23
#define IPU_ADC_CHA_START_TIME_WID              9

// ADC_DISP0_CONF
// ADC_DISP1_CONF
// ADC_DISP2_CONF
#define IPU_ADC_DISP_CONF_DISP_SL_WID           12
#define IPU_ADC_DISP_CONF_DISP_TYPE_WID         2
#define IPU_ADC_DISP_CONF_DISP_DATA_WIDTH_WID   1
#define IPU_ADC_DISP_CONF_DISP_DATA_MAP_WID     1

// ADC_DISP0_RD_AP
#define IPU_ADC_DISP0_RD_AP_DISP0_ACK_PTRN_WID  24

// ADC_DISP0_RDM
#define IPU_ADC_DISP0_RDM_DISP0_MASK_ACK_DATA_WID   24


// ADC_DISP0_SS
// ADC_DISP1_SS
// ADC_DISP2_SS
#define IPU_ADC_DISP_SS_SCREEN_WIDTH_WID        10
#define IPU_ADC_DISP_SS_SCREEN_HEIGHT_WID       10

// ADC_DISP_VSYNC
#define IPU_ADC_DISP_VSYNC_DISP0_VSYNC_MODE_WID     2
#define IPU_ADC_DISP_VSYNC_DISP12_VSYNC_MODE_WID    2
#define IPU_ADC_DISP_VSYNC_DISP12_VSYNC_SEL_WID     1
#define IPU_ADC_DISP_VSYNC_DISP_LN_WT_WID           10
#define IPU_ADC_DISP_VSYNC_DISP0_VSYNC_WIDTH_WID    6
#define IPU_ADC_DISP_VSYNC_DISP0_VSYNC_WIDTH_L_WID  1
#define IPU_ADC_DISP_VSYNC_DISP12_VSYNC_WIDTH_WID   6
#define IPU_ADC_DISP_VSYNC_DISP12_VSYNC_WIDTH_L_WID 1


// DI_DISP_IF_CONF
#define IPU_DI_DISP_IF_CONF_DISP0_EN_WID                1
#define IPU_DI_DISP_IF_CONF_DISP0_IF_MODE_WID           2
#define IPU_DI_DISP_IF_CONF_DISP0_PAR_BURST_MODE_WID    2
#define IPU_DI_DISP_IF_CONF_DISP1_EN_WID                1
#define IPU_DI_DISP_IF_CONF_DISP1_IF_MODE_WID           3
#define IPU_DI_DISP_IF_CONF_DISP1_PAR_BURST_MODE_WID    2
#define IPU_DI_DISP_IF_CONF_DISP2_EN_WID                1
#define IPU_DI_DISP_IF_CONF_DISP2_IF_MODE_WID           3
#define IPU_DI_DISP_IF_CONF_DISP2_PAR_BURST_MODE_WID    2
#define IPU_DI_DISP_IF_CONF_DISP3_DATAMASK_WID          1
#define IPU_DI_DISP_IF_CONF_DISP3_CLK_SEL_WID           1
#define IPU_DI_DISP_IF_CONF_DISP3_CLK_IDLE_WID          1
#define IPU_DI_DISP_IF_CONF_DISP012_DEAD_CLK_NUM_WID    4


// DI_DISP_SIG_POL
#define IPU_DI_DISP_SIG_POL_D0_DATA_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D0_CS_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D0_PAR_RS_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D0_WR_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D0_RD_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D0_VSYNC_POL_WID            1
#define IPU_DI_DISP_SIG_POL_D12_VSYNC_POL_WID           1
//#define IPU_DI_DISP_SIG_POL_RESERVED                  1
#define IPU_DI_DISP_SIG_POL_D1_DATA_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D1_CS_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D1_PAR_RS_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D1_WR_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D1_RD_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D1_SD_D_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D1_SD_CLK_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D1_SER_RS_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D2_DATA_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D2_CS_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D2_PAR_RS_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D2_WR_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D2_RD_POL_WID               1
#define IPU_DI_DISP_SIG_POL_D2_SD_D_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D2_SD_CLK_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D2_SER_RS_POL_WID           1
#define IPU_DI_DISP_SIG_POL_D3_DATA_POL_WID             1
#define IPU_DI_DISP_SIG_POL_D3_CLK_POL_WID              1
#define IPU_DI_DISP_SIG_POL_D3_DRDY_SHARP_POL_WID       1
#define I