mxarm11_ipu.h

freescale i.mx31 BSP CE5.0全部源码

#define IPU_DI_DISP1_CB2_MAP_MC12_OFFS2_LSH     26

// DI_DISP2_DB0_MAP
#define IPU_DI_DISP2_DB0_MAP_MD20_M0_LSH        0
#define IPU_DI_DISP2_DB0_MAP_MD20_M1_LSH        2
#define IPU_DI_DISP2_DB0_MAP_MD20_M2_LSH        4
#define IPU_DI_DISP2_DB0_MAP_MD20_M3_LSH        6
#define IPU_DI_DISP2_DB0_MAP_MD20_M4_LSH        8
#define IPU_DI_DISP2_DB0_MAP_MD20_M5_LSH        10
#define IPU_DI_DISP2_DB0_MAP_MD20_M6_LSH        12
#define IPU_DI_DISP2_DB0_MAP_MD20_M7_LSH        14
#define IPU_DI_DISP2_DB0_MAP_MD20_OFFS0_LSH     16
#define IPU_DI_DISP2_DB0_MAP_MD20_OFFS1_LSH     21
#define IPU_DI_DISP2_DB0_MAP_MD20_OFFS2_LSH     26

// DI_DISP2_DB1_MAP
#define IPU_DI_DISP2_DB1_MAP_MD21_M0_LSH        0
#define IPU_DI_DISP2_DB1_MAP_MD21_M1_LSH        2
#define IPU_DI_DISP2_DB1_MAP_MD21_M2_LSH        4
#define IPU_DI_DISP2_DB1_MAP_MD21_M3_LSH        6
#define IPU_DI_DISP2_DB1_MAP_MD21_M4_LSH        8
#define IPU_DI_DISP2_DB1_MAP_MD21_M5_LSH        10
#define IPU_DI_DISP2_DB1_MAP_MD21_M6_LSH        12
#define IPU_DI_DISP2_DB1_MAP_MD21_M7_LSH        14
#define IPU_DI_DISP2_DB1_MAP_MD21_OFFS0_LSH     16
#define IPU_DI_DISP2_DB1_MAP_MD21_OFFS1_LSH     21
#define IPU_DI_DISP2_DB1_MAP_MD21_OFFS2_LSH     26

// DI_DISP2_DB2_MAP
#define IPU_DI_DISP2_DB2_MAP_MD22_M0_LSH        0
#define IPU_DI_DISP2_DB2_MAP_MD22_M1_LSH        2
#define IPU_DI_DISP2_DB2_MAP_MD22_M2_LSH        4
#define IPU_DI_DISP2_DB2_MAP_MD22_M3_LSH        6
#define IPU_DI_DISP2_DB2_MAP_MD22_M4_LSH        8
#define IPU_DI_DISP2_DB2_MAP_MD22_M5_LSH        10
#define IPU_DI_DISP2_DB2_MAP_MD22_M6_LSH        12
#define IPU_DI_DISP2_DB2_MAP_MD22_M7_LSH        14
#define IPU_DI_DISP2_DB2_MAP_MD22_OFFS0_LSH     16
#define IPU_DI_DISP2_DB2_MAP_MD22_OFFS1_LSH     21
#define IPU_DI_DISP2_DB2_MAP_MD22_OFFS2_LSH     26

// DI_DISP2_CB0_MAP
#define IPU_DI_DISP2_CB0_MAP_MC20_M0_LSH        0
#define IPU_DI_DISP2_CB0_MAP_MC20_M1_LSH        2
#define IPU_DI_DISP2_CB0_MAP_MC20_M2_LSH        4
#define IPU_DI_DISP2_CB0_MAP_MC20_M3_LSH        6
#define IPU_DI_DISP2_CB0_MAP_MC20_M4_LSH        8
#define IPU_DI_DISP2_CB0_MAP_MC20_M5_LSH        10
#define IPU_DI_DISP2_CB0_MAP_MC20_M6_LSH        12
#define IPU_DI_DISP2_CB0_MAP_MC20_M7_LSH        14
#define IPU_DI_DISP2_CB0_MAP_MC20_OFFS0_LSH     16
#define IPU_DI_DISP2_CB0_MAP_MC20_OFFS1_LSH     21
#define IPU_DI_DISP2_CB0_MAP_MC20_OFFS2_LSH     26

// DI_DISP2_CB1_MAP
#define IPU_DI_DISP2_CB1_MAP_MC21_M0_LSH        0
#define IPU_DI_DISP2_CB1_MAP_MC21_M1_LSH        2
#define IPU_DI_DISP2_CB1_MAP_MC21_M2_LSH        4
#define IPU_DI_DISP2_CB1_MAP_MC21_M3_LSH        6
#define IPU_DI_DISP2_CB1_MAP_MC21_M4_LSH        8
#define IPU_DI_DISP2_CB1_MAP_MC21_M5_LSH        10
#define IPU_DI_DISP2_CB1_MAP_MC21_M6_LSH        12
#define IPU_DI_DISP2_CB1_MAP_MC21_M7_LSH        14
#define IPU_DI_DISP2_CB1_MAP_MC21_OFFS0_LSH     16
#define IPU_DI_DISP2_CB1_MAP_MC21_OFFS1_LSH     21
#define IPU_DI_DISP2_CB1_MAP_MC21_OFFS2_LSH     26

// DI_DISP2_CB2_MAP
#define IPU_DI_DISP2_CB2_MAP_MC22_M0_LSH        0
#define IPU_DI_DISP2_CB2_MAP_MC22_M1_LSH        2
#define IPU_DI_DISP2_CB2_MAP_MC22_M2_LSH        4
#define IPU_DI_DISP2_CB2_MAP_MC22_M3_LSH        6
#define IPU_DI_DISP2_CB2_MAP_MC22_M4_LSH        8
#define IPU_DI_DISP2_CB2_MAP_MC22_M5_LSH        10
#define IPU_DI_DISP2_CB2_MAP_MC22_M6_LSH        12
#define IPU_DI_DISP2_CB2_MAP_MC22_M7_LSH        14
#define IPU_DI_DISP2_CB2_MAP_MC22_OFFS0_LSH     16
#define IPU_DI_DISP2_CB2_MAP_MC22_OFFS1_LSH     21
#define IPU_DI_DISP2_CB2_MAP_MC22_OFFS2_LSH     26

// DI_DISP3_B0_MAP
#define IPU_DI_DISP3_B0_MAP_M30_M0_LSH          0
#define IPU_DI_DISP3_B0_MAP_M30_M1_LSH          2
#define IPU_DI_DISP3_B0_MAP_M30_M2_LSH          4
#define IPU_DI_DISP3_B0_MAP_M30_M3_LSH          6
#define IPU_DI_DISP3_B0_MAP_M30_M4_LSH          8
#define IPU_DI_DISP3_B0_MAP_M30_M5_LSH          10
#define IPU_DI_DISP3_B0_MAP_M30_M6_LSH          12
#define IPU_DI_DISP3_B0_MAP_M30_M7_LSH          14
#define IPU_DI_DISP3_B0_MAP_M30_OFFS0_LSH       16
#define IPU_DI_DISP3_B0_MAP_M30_OFFS1_LSH       21
#define IPU_DI_DISP3_B0_MAP_M30_OFFS2_LSH       26

// DI_DISP3_B1_MAP
#define IPU_DI_DISP3_B1_MAP_M31_M0_LSH          0
#define IPU_DI_DISP3_B1_MAP_M31_M1_LSH          2
#define IPU_DI_DISP3_B1_MAP_M31_M2_LSH          4
#define IPU_DI_DISP3_B1_MAP_M31_M3_LSH          6
#define IPU_DI_DISP3_B1_MAP_M31_M4_LSH          8
#define IPU_DI_DISP3_B1_MAP_M31_M5_LSH          10
#define IPU_DI_DISP3_B1_MAP_M31_M6_LSH          12
#define IPU_DI_DISP3_B1_MAP_M31_M7_LSH          14
#define IPU_DI_DISP3_B1_MAP_M31_OFFS0_LSH       16
#define IPU_DI_DISP3_B1_MAP_M31_OFFS1_LSH       21
#define IPU_DI_DISP3_B1_MAP_M31_OFFS2_LSH       26

// DI_DISP3_B2_MAP
#define IPU_DI_DISP3_B2_MAP_M32_M0_LSH          0
#define IPU_DI_DISP3_B2_MAP_M32_M1_LSH          2
#define IPU_DI_DISP3_B2_MAP_M32_M2_LSH          4
#define IPU_DI_DISP3_B2_MAP_M32_M3_LSH          6
#define IPU_DI_DISP3_B2_MAP_M32_M4_LSH          8
#define IPU_DI_DISP3_B2_MAP_M32_M5_LSH          10
#define IPU_DI_DISP3_B2_MAP_M32_M6_LSH          12
#define IPU_DI_DISP3_B2_MAP_M32_M7_LSH          14
#define IPU_DI_DISP3_B2_MAP_M32_OFFS0_LSH       16
#define IPU_DI_DISP3_B2_MAP_M32_OFFS1_LSH       21
#define IPU_DI_DISP3_B2_MAP_M32_OFFS2_LSH       26

// DI_DISP_ACC_CC
#define IPU_DI_DISP_ACC_CC_DISP0_IF_CLK_CNT_D_LSH   0
#define IPU_DI_DISP_ACC_CC_DISP0_IF_CLK_CNT_C_LSH   2
#define IPU_DI_DISP_ACC_CC_DISP1_IF_CLK_CNT_D_LSH   4
#define IPU_DI_DISP_ACC_CC_DISP1_IF_CLK_CNT_C_LSH   6
#define IPU_DI_DISP_ACC_CC_DISP2_IF_CLK_CNT_D_LSH   8
#define IPU_DI_DISP_ACC_CC_DISP2_IF_CLK_CNT_C_LSH   10
#define IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D_LSH   12

// DI_DISP_LLA_CONF
#define IPU_DI_DISP_LLA_CONF_DRCT_RS_LSH        0
#define IPU_DI_DISP_LLA_CONF_DRCT_DISP_NUM_LSH  1
#define IPU_DI_DISP_LLA_CONF_DRCT_LOCK_LSH      3
#define IPU_DI_DISP_LLA_CONF_DRCT_MAP_DC_LSH    4
#define IPU_DI_DISP_LLA_CONF_DRCT_BE_MODE_LSH   5

// DI_DISP_LLA_DATA
#define IPU_DI_DISP_LLA_DATA_LLA_DATA_LSH       0


//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------

// IPU_CONF
#define IPU_IPU_CONF_CSI_EN_WID                 1
#define IPU_IPU_CONF_IC_EN_WID                  1
#define IPU_IPU_CONF_ROT_EN_WID                 1
#define IPU_IPU_CONF_PF_EN_WID                  1
#define IPU_IPU_CONF_SDC_EN_WID                 1
#define IPU_IPU_CONF_ADC_EN_WID                 1
#define IPU_IPU_CONF_DI_EN_WID                  1
#define IPU_IPU_CONF_DU_EN_WID                  1
#define IPU_IPU_CONF_PXL_ENDIAN_WID             1

// IPU DMA Channel ID used in the various IPU registers
#define IPU_DMA_CHA_DMAIC_0_WID                 1
#define IPU_DMA_CHA_DMAIC_1_WID                 1
#define IPU_DMA_CHA_DMAADC_0_WID                1
#define IPU_DMA_CHA_DMAIC_2_WID                 1
#define IPU_DMA_CHA_DMAADC_1_WID                1
#define IPU_DMA_CHA_DMAIC_3_WID                 1
#define IPU_DMA_CHA_DMAIC_4_WID                 1
#define IPU_DMA_CHA_DMAIC_5_WID                 1
#define IPU_DMA_CHA_DMAIC_6_WID                 1
#define IPU_DMA_CHA_DMAIC_7_WID                 1
#define IPU_DMA_CHA_DMAIC_8_WID                 1
#define IPU_DMA_CHA_DMAIC_9_WID                 1
#define IPU_DMA_CHA_DMAIC_10_WID                1
#define IPU_DMA_CHA_DMAIC_11_WID                1
#define IPU_DMA_CHA_DMAIC_12_WID                1
#define IPU_DMA_CHA_DMAIC_13_WID                1
#define IPU_DMA_CHA_DMASDC_0_WID                1
#define IPU_DMA_CHA_DMASDC_1_WID                1
#define IPU_DMA_CHA_DMASDC_2_WID                1
#define IPU_DMA_CHA_DMASDC_3_WID                1
#define IPU_DMA_CHA_DMAADC_2_WID                1
#define IPU_DMA_CHA_DMAADC_3_WID                1
#define IPU_DMA_CHA_DMAADC_4_WID                1
#define IPU_DMA_CHA_DMAADC_5_WID                1
#define IPU_DMA_CHA_DMAADC_6_WID                1
#define IPU_DMA_CHA_DMAADC_7_WID                1
#define IPU_DMA_CHA_DMAPF_0_WID                 1
#define IPU_DMA_CHA_DMAPF_1_WID                 1
#define IPU_DMA_CHA_DMAPF_2_WID                 1
#define IPU_DMA_CHA_DMAPF_3_WID                 1
#define IPU_DMA_CHA_DMAPF_4_WID                 1
#define IPU_DMA_CHA_DMAPF_5_WID                 1
#define IPU_DMA_CHA_DMAPF_6_WID                 1
#define IPU_DMA_CHA_DMAPF_7_WID                 1

// IPU_FS_PROC_FLOW
#define IPU_IPU_FS_PROC_FLOW_ENC_IN_VALID_WID       1
#define IPU_IPU_FS_PROC_FLOW_VF_IN_VALID_WID        1
#define IPU_IPU_FS_PROC_FLOW_PRPENC_DEST_SEL_WID    1
#define IPU_IPU_FS_PROC_FLOW_PRPENC_ROT_SRC_SEL_WID 1
#define IPU_IPU_FS_PROC_FLOW_PRPVF_ROT_SRC_SEL_WID  1
#define IPU_IPU_FS_PROC_FLOW_PP_SRC_SEL_WID         2
#define IPU_IPU_FS_PROC_FLOW_PP_ROT_SRC_SEL_WID     2
#define IPU_IPU_FS_PROC_FLOW_PF_DEST_SEL_WID        2
#define IPU_IPU_FS_PROC_FLOW_PRPVF_DEST_SEL_WID     3
#define IPU_IPU_FS_PROC_FLOW_PRPVF_ROT_DEST_SEL_WID 3
#define IPU_IPU_FS_PROC_FLOW_PP_DEST_SEL_WID        3
#define IPU_IPU_FS_PROC_FLOW_PP_ROT_DEST_SEL_WID    3

// IPU_FS_DISP_FLOW
#define IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL_WID   3
#define IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL_WID   3
#define IPU_IPU_FS_DISP_FLOW_ADC2_SRC_SEL_WID   3
#define IPU_IPU_FS_DISP_FLOW_ADC3_SRC_SEL_WID   3
#define IPU_IPU_FS_DISP_FLOW_AUTO_REF_PER_WID   10

// IPU_IMA_ADDR
#define IPU_IPU_IMA_ADDR_WORD_NU_WID            3
#define IPU_IPU_IMA_ADDR_ROW_NU_WID             13
#define IPU_IPU_IMA_ADDR_MEM_NU_WID             4

// IPU_IMA_DATA

//...parameters for YUV/RGB  interleaved - 1st 132 bit word

//...0th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_XV_WID       10
#define IPU_IPU_IMA_DATA_PARAM_YV_WID       10
#define IPU_IPU_IMA_DATA_PARAM_XB_WID       12

//...1st 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_YB_WID       12
#define IPU_IPU_IMA_DATA_PARAM_SCE_WID      1
#define IPU_IPU_IMA_DATA_PARAM_NSB_WID      1
//  1 - reserved bit                     
#define IPU_IPU_IMA_DATA_PARAM_LNPB_WID     6
#define IPU_IPU_IMA_DATA_PARAM_SX_WID       10
#define IPU_IPU_IMA_DATA_PARAM_LOW_SY_WID   1

//...2nd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_SY_WID  9
#define IPU_IPU_IMA_DATA_PARAM_NS_WID       10
#define IPU_IPU_IMA_DATA_PARAM_SM_WID       10
#define IPU_IPU_IMA_DATA_PARAM_LOW_SDX_WID  3

//...3rd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_SDX_WID 2
#define IPU_IPU_IMA_DATA_PARAM_SDY_WID      5
#define IPU_IPU_IMA_DATA_PARAM_SDRX_WID     1
#define IPU_IPU_IMA_DATA_PARAM_SDRY_WID     1
#define IPU_IPU_IMA_DATA_PARAM_SCRQ_WID     1
//  2 - reserved bits
#define IPU_IPU_IMA_DATA_PARAM_FW_WID       12
#define IPU_IPU_IMA_DATA_PARAM_LOW_FH_WID   8

//...4th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_FH_WID  4

//...parameters for YUV/RGB interleaved - 2nd 132 bit word

//...0th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_EBA0_WID     32

//...1st 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_EBA1_WID     32

//...2nd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_BPP_WID      3
#define IPU_IPU_IMA_DATA_PARAM_SL_WID       14
#define IPU_IPU_IMA_DATA_PARAM_PFS_WID      3
#define IPU_IPU_IMA_DATA_PARAM_BAM_WID      3
//  2 - reserved bits
#define IPU_IPU_IMA_DATA_PARAM_NPB_WID      6
//  1 - reserved bit                     

//...3rd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_SAT_WID      2
#define IPU_IPU_IMA_DATA_PARAM_SCC_WID      1
#define IPU_IPU_IMA_DATA_PARAM_OFS0_WID     5
#define IPU_IPU_IMA_DATA_PARAM_OFS1_WID     5
#define IPU_IPU_IMA_DATA_PARAM_OFS2_WID     5
#define IPU_IPU_IMA_DATA_PARAM_OFS3_WID     5
#define IPU_IPU_IMA_DATA_PARAM_WID0_WID     3
#define IPU_IPU_IMA_DATA_PARAM_WID1_WID     3
#define IPU_IPU_IMA_DATA_PARAM_WID2_WID     3

//...4th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_WID3_WID     3
#define IPU_IPU_IMA_DATA_PARAM_DEC_SEL_WID  1


// IPU_INT_CTRL_1
#define IPU_IPU_INT_CTRL_1_DMAIC_0_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_1_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_2_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_3_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_4_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_5_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_6_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_7_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_8_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_9_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAIC_10_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAIC_11_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAIC_12_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAIC_13_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMASDC_0_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMASDC_1_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMASDC_2_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMASDC_3_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_2_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_3_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_4_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_5_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_6_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAADC_7_EOF_EN_WID  1
#define IPU_IPU_INT_CTRL_1_DMAPF_0_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_1_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_2_EOF_EN_WID   1
#define IPU_IPU_INT_CTRL_1_DMAPF_3_EOF_EN_WID   1