mxarm11_ipu.h

freescale i.mx31 BSP CE5.0全部源码

#define IPU_DMA_CHA_DMAADC_0_LSH                1
#define IPU_DMA_CHA_DMAIC_2_LSH                 2
#define IPU_DMA_CHA_DMAADC_1_LSH                2
#define IPU_DMA_CHA_DMAIC_3_LSH                 3
#define IPU_DMA_CHA_DMAIC_4_LSH                 4
#define IPU_DMA_CHA_DMAIC_5_LSH                 5
#define IPU_DMA_CHA_DMAIC_6_LSH                 6
#define IPU_DMA_CHA_DMAIC_7_LSH                 7
#define IPU_DMA_CHA_DMAIC_8_LSH                 8
#define IPU_DMA_CHA_DMAIC_9_LSH                 9
#define IPU_DMA_CHA_DMAIC_10_LSH                10
#define IPU_DMA_CHA_DMAIC_11_LSH                11
#define IPU_DMA_CHA_DMAIC_12_LSH                12
#define IPU_DMA_CHA_DMAIC_13_LSH                13
#define IPU_DMA_CHA_DMASDC_0_LSH                14
#define IPU_DMA_CHA_DMASDC_1_LSH                15
#define IPU_DMA_CHA_DMASDC_2_LSH                16
#define IPU_DMA_CHA_DMASDC_3_LSH                17
#define IPU_DMA_CHA_DMAADC_2_LSH                18
#define IPU_DMA_CHA_DMAADC_3_LSH                19
#define IPU_DMA_CHA_DMAADC_4_LSH                20
#define IPU_DMA_CHA_DMAADC_5_LSH                21
#define IPU_DMA_CHA_DMAADC_6_LSH                22
#define IPU_DMA_CHA_DMAADC_7_LSH                23
#define IPU_DMA_CHA_DMAPF_0_LSH                 24
#define IPU_DMA_CHA_DMAPF_1_LSH                 25
#define IPU_DMA_CHA_DMAPF_2_LSH                 26
#define IPU_DMA_CHA_DMAPF_3_LSH                 27
#define IPU_DMA_CHA_DMAPF_4_LSH                 28
#define IPU_DMA_CHA_DMAPF_5_LSH                 29
#define IPU_DMA_CHA_DMAPF_6_LSH                 30
#define IPU_DMA_CHA_DMAPF_7_LSH                 31

// IPU_FS_PROC_FLOW
#define IPU_IPU_FS_PROC_FLOW_ENC_IN_VALID_LSH       0
#define IPU_IPU_FS_PROC_FLOW_VF_IN_VALID_LSH        1
#define IPU_IPU_FS_PROC_FLOW_PRPENC_DEST_SEL_LSH    4
#define IPU_IPU_FS_PROC_FLOW_PRPENC_ROT_SRC_SEL_LSH 5
#define IPU_IPU_FS_PROC_FLOW_PRPVF_ROT_SRC_SEL_LSH  6
#define IPU_IPU_FS_PROC_FLOW_PP_SRC_SEL_LSH         8
#define IPU_IPU_FS_PROC_FLOW_PP_ROT_SRC_SEL_LSH     10
#define IPU_IPU_FS_PROC_FLOW_PF_DEST_SEL_LSH        12
#define IPU_IPU_FS_PROC_FLOW_PRPVF_DEST_SEL_LSH     16
#define IPU_IPU_FS_PROC_FLOW_PRPVF_ROT_DEST_SEL_LSH 20
#define IPU_IPU_FS_PROC_FLOW_PP_DEST_SEL_LSH        24
#define IPU_IPU_FS_PROC_FLOW_PP_ROT_DEST_SEL_LSH    28

// IPU_FS_DISP_FLOW
#define IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL_LSH   0
#define IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL_LSH   4
#define IPU_IPU_FS_DISP_FLOW_ADC2_SRC_SEL_LSH   8
#define IPU_IPU_FS_DISP_FLOW_ADC3_SRC_SEL_LSH   12
#define IPU_IPU_FS_DISP_FLOW_AUTO_REF_PER_LSH   16

// IPU_IMA_ADDR
#define IPU_IPU_IMA_ADDR_WORD_NU_LSH            0
#define IPU_IPU_IMA_ADDR_ROW_NU_LSH             3
#define IPU_IPU_IMA_ADDR_MEM_NU_LSH             16


// IPU_IMA_DATA 

//...parameters for YUV/RGB  interleaved - 1st 132 bit word

//...0th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_XV_LSH       0
#define IPU_IPU_IMA_DATA_PARAM_YV_LSH       10
#define IPU_IPU_IMA_DATA_PARAM_XB_LSH       20

//...1st 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_YB_LSH       (32 - 32)
#define IPU_IPU_IMA_DATA_PARAM_SCE_LSH      (44 - 32)
// 1 - reserved bit                   
#define IPU_IPU_IMA_DATA_PARAM_NSB_LSH      (46 - 32)
#define IPU_IPU_IMA_DATA_PARAM_LNPB_LSH     (47 - 32)
#define IPU_IPU_IMA_DATA_PARAM_SX_LSH       (53 - 32)
#define IPU_IPU_IMA_DATA_PARAM_LOW_SY_LSH   (63 - 32)

//...2nd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_SY_LSH  64
#define IPU_IPU_IMA_DATA_PARAM_NS_LSH       (73 - 64)
#define IPU_IPU_IMA_DATA_PARAM_SM_LSH       (83 - 64)
#define IPU_IPU_IMA_DATA_PARAM_LOW_SDX_LSH  (93 - 64)

//...3rd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_SDX_LSH (96 - 96)
#define IPU_IPU_IMA_DATA_PARAM_SDY_LSH      (98 - 96)
#define IPU_IPU_IMA_DATA_PARAM_SDRX_LSH     (103 - 96)
#define IPU_IPU_IMA_DATA_PARAM_SDRY_LSH     (104 - 96)
#define IPU_IPU_IMA_DATA_PARAM_SCRQ_LSH     (105 - 96)
// 2 - reserved bits
#define IPU_IPU_IMA_DATA_PARAM_FW_LSH       (108 - 96)
#define IPU_IPU_IMA_DATA_PARAM_LOW_FH_LSH   (120 - 96)

//...4th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_HIGH_FH_LSH  (128 - 128)


//...parameters for YUV/RGB interleaved - 2nd 132 bit word

//...0th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_EBA0_LSH     0

//...1st 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_EBA1_LSH     (32 - 32)

//...2nd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_BPP_LSH      (64 - 64)
#define IPU_IPU_IMA_DATA_PARAM_SL_LSH       (67 - 64)
#define IPU_IPU_IMA_DATA_PARAM_PFS_LSH      (81 - 64)
#define IPU_IPU_IMA_DATA_PARAM_BAM_LSH      (84 - 64)
//  2 - reserved bits
#define IPU_IPU_IMA_DATA_PARAM_NPB_LSH      (89 - 64)
//  1 - reserved bit

//...3rd 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_SAT_LSH      (96 - 96)
#define IPU_IPU_IMA_DATA_PARAM_SCC_LSH      (98 - 96)
#define IPU_IPU_IMA_DATA_PARAM_OFS0_LSH     (99 - 96)
#define IPU_IPU_IMA_DATA_PARAM_OFS1_LSH     (104 - 96)
#define IPU_IPU_IMA_DATA_PARAM_OFS2_LSH     (109 - 96)
#define IPU_IPU_IMA_DATA_PARAM_OFS3_LSH     (114 - 96)
#define IPU_IPU_IMA_DATA_PARAM_WID0_LSH     (119 - 96)
#define IPU_IPU_IMA_DATA_PARAM_WID1_LSH     (122 - 96)
#define IPU_IPU_IMA_DATA_PARAM_WID2_LSH     (125 - 96)

//...4th 32 bit word
#define IPU_IPU_IMA_DATA_PARAM_WID3_LSH     (128 - 128)
#define IPU_IPU_IMA_DATA_PARAM_DEC_SEL_LSH  (131 - 128)

// IPU_INT_CTRL_1
#define IPU_IPU_INT_CTRL_1_DMAIC_0_EOF_EN_LSH   0
#define IPU_IPU_INT_CTRL_1_DMAIC_1_EOF_EN_LSH   1
#define IPU_IPU_INT_CTRL_1_DMAIC_2_EOF_EN_LSH   2
#define IPU_IPU_INT_CTRL_1_DMAIC_3_EOF_EN_LSH   3
#define IPU_IPU_INT_CTRL_1_DMAIC_4_EOF_EN_LSH   4
#define IPU_IPU_INT_CTRL_1_DMAIC_5_EOF_EN_LSH   5
#define IPU_IPU_INT_CTRL_1_DMAIC_6_EOF_EN_LSH   6
#define IPU_IPU_INT_CTRL_1_DMAIC_7_EOF_EN_LSH   7
#define IPU_IPU_INT_CTRL_1_DMAIC_8_EOF_EN_LSH   8
#define IPU_IPU_INT_CTRL_1_DMAIC_9_EOF_EN_LSH   9
#define IPU_IPU_INT_CTRL_1_DMAIC_10_EOF_EN_LSH  10
#define IPU_IPU_INT_CTRL_1_DMAIC_11_EOF_EN_LSH  11
#define IPU_IPU_INT_CTRL_1_DMAIC_12_EOF_EN_LSH  12
#define IPU_IPU_INT_CTRL_1_DMAIC_13_EOF_EN_LSH  13
#define IPU_IPU_INT_CTRL_1_DMASDC_0_EOF_EN_LSH  14
#define IPU_IPU_INT_CTRL_1_DMASDC_1_EOF_EN_LSH  15
#define IPU_IPU_INT_CTRL_1_DMASDC_2_EOF_EN_LSH  16
#define IPU_IPU_INT_CTRL_1_DMASDC_3_EOF_EN_LSH  17
#define IPU_IPU_INT_CTRL_1_DMAADC_2_EOF_EN_LSH  18
#define IPU_IPU_INT_CTRL_1_DMAADC_3_EOF_EN_LSH  19
#define IPU_IPU_INT_CTRL_1_DMAADC_4_EOF_EN_LSH  20
#define IPU_IPU_INT_CTRL_1_DMAADC_5_EOF_EN_LSH  21
#define IPU_IPU_INT_CTRL_1_DMAADC_6_EOF_EN_LSH  22
#define IPU_IPU_INT_CTRL_1_DMAADC_7_EOF_EN_LSH  23
#define IPU_IPU_INT_CTRL_1_DMAPF_0_EOF_EN_LSH   24
#define IPU_IPU_INT_CTRL_1_DMAPF_1_EOF_EN_LSH   25
#define IPU_IPU_INT_CTRL_1_DMAPF_2_EOF_EN_LSH   26
#define IPU_IPU_INT_CTRL_1_DMAPF_3_EOF_EN_LSH   27
#define IPU_IPU_INT_CTRL_1_DMAPF_4_EOF_EN_LSH   28
#define IPU_IPU_INT_CTRL_1_DMAPF_5_EOF_EN_LSH   29
#define IPU_IPU_INT_CTRL_1_DMAPF_6_EOF_EN_LSH   30
#define IPU_IPU_INT_CTRL_1_DMAPF_7_EOF_EN_LSH   31


// IPU CSI Registers
#define IPU_CSI_SENS_CONF_VSYNC_POL_LSH         0
#define IPU_CSI_SENS_CONF_HSYNC_POL_LSH         1
#define IPU_CSI_SENS_CONF_DATA_POL_LSH          2
#define IPU_CSI_SENS_CONF_DISP_PIX_CLK_POL_LSH  3
#define IPU_CSI_SENS_CONF_SENS_PRTCL_LSH        4
#define IPU_CSI_SENS_CONF_SENS_CLK_SRC_LSH      7
#define IPU_CSI_SENS_CONF_SENS_DATA_FORMAT_LSH  8
#define IPU_CSI_SENS_CONF_DATA_WIDTH_LSH        10
#define IPU_CSI_SENS_CONF_EXT_VSYNC_LSH         15
#define IPU_CSI_SENS_CONF_DIV_RATIO_LSH         16
#define IPU_CSI_SENS_CONF_MCLK_PIXCLK_RATIO_LSH 24

#define IPU_CSI_SENS_FRM_SIZE_SENS_FRM_WIDTH_LSH  0
#define IPU_CSI_SENS_FRM_SIZE_SENS_FRM_HEIGHT_LSH 16

#define IPU_CSI_ACT_FRM_SIZE_ACT_FRM_WIDTH_LSH  0
#define IPU_CSI_ACT_FRM_SIZE_ACT_FRM_HEIGHT_LSH 16

#define IPU_CSI_OUT_FRM_CTRL_VSC_LSH            0
#define IPU_CSI_OUT_FRM_CTRL_HSC_LSH            8
#define IPU_CSI_OUT_FRM_CTRL_SKIP_ENC_LSH       16
#define IPU_CSI_OUT_FRM_CTRL_SKIP_VF_LSH        21
#define IPU_CSI_OUT_FRM_CTRL_IC_TV_MODE_LSH     26
#define IPU_CSI_OUT_FRM_CTRL_VERT_DWNS_LSH      28
#define IPU_CSI_OUT_FRM_CTRL_HORZ_DWNS_LSH      29

#define IPU_CSI_TST_CTRL_PG_R_VALUE_LSH         0
#define IPU_CSI_TST_CTRL_PG_G_VALUE_LSH         8
#define IPU_CSI_TST_CTRL_PG_B_VALUE_LSH         16
#define IPU_CSI_TST_CTRL_TEST_GEN_MODE_LSH      24

#define IPU_CSI_CCIR_CODE_1_END_FLD0_BLNK_1ST_LSH   0
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_BLNK_1ST_LSH  3
#define IPU_CSI_CCIR_CODE_1_END_FLD0_BLNK_2ND_LSH   6
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_BLNK_2ND_LSH  9
#define IPU_CSI_CCIR_CODE_1_END_FLD0_ACTV_LSH       16
#define IPU_CSI_CCIR_CODE_1_STRT_FLD0_ACTV_LSH      19
#define IPU_CSI_CCIR_CODE_1_CCIR_ERR_DET_EN_LSH     24

#define IPU_CSI_CCIR_CODE_2_END_FLD1_BLNK_1ST_LSH   0
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_BLNK_1ST_LSH  3
#define IPU_CSI_CCIR_CODE_2_END_FLD1_BLNK_2ND_LSH   6
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_BLNK_2ND_LSH  9
#define IPU_CSI_CCIR_CODE_2_END_FLD1_ACTV_LSH       16
#define IPU_CSI_CCIR_CODE_2_STRT_FLD1_ACTV_LSH      19

#define IPU_CSI_CCIR_CODE_3_CCIR_PRECOM_LSH         0

#define IPU_CSI_FLASH_STROBE_1_CLOCK_SEL_LSH           0
#define IPU_CSI_FLASH_STROBE_1_SENSE_ROW_DURATION_LSH  16

#define IPU_CSI_FLASH_STROBE_2_STROBE_EN_LSH           0
#define IPU_CSI_FLASH_STROBE_2_STROBE_POL_LSH          1
#define IPU_CSI_FLASH_STROBE_2_STROBE_START_TIME_LSH   3
#define IPU_CSI_FLASH_STROBE_2_STROBE_DURATION_LSH     16


// IPU IC Registers
#define IPU_IC_CONF_PRPENC_EN_LSH               0
#define IPU_IC_CONF_PRPENC_CSC1_LSH             1
#define IPU_IC_CONF_PRPENC_ROT_EN_LSH           2
#define IPU_IC_CONF_PRPVF_EN_LSH                8
#define IPU_IC_CONF_PRPVF_CSC1_LSH              9
#define IPU_IC_CONF_PRPVF_CSC2_LSH              10
#define IPU_IC_CONF_PRPVF_CMB_LSH               11
#define IPU_IC_CONF_PRPVF_ROT_EN_LSH            12
#define IPU_IC_CONF_PP_EN_LSH                   16
#define IPU_IC_CONF_PP_CSC1_LSH                 17
#define IPU_IC_CONF_PP_CSC2_LSH                 18
#define IPU_IC_CONF_PP_CMB_LSH                  19
#define IPU_IC_CONF_PP_ROT_EN_LSH               20
#define IPU_IC_CONF_IC_GLB_LOC_A_LSH            28
#define IPU_IC_CONF_IC_KEY_COLOR_EN_LSH         29
#define IPU_IC_CONF_RWS_EN_LSH                  30
#define IPU_IC_CONF_CSI_MEM_WR_EN_LSH           31

#define IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H_LSH    0
#define IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H_LSH    14
#define IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V_LSH    16
#define IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V_LSH    30

#define IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H_LSH      0
#define IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H_LSH      14
#define IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V_LSH      16
#define IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V_LSH      30

#define IPU_IC_PP_RSC_PP_RS_R_H_LSH             0
#define IPU_IC_PP_RSC_PP_DS_R_H_LSH             14
#define IPU_IC_PP_RSC_PP_RS_R_V_LSH             16
#define IPU_IC_PP_RSC_PP_DS_R_V_LSH             30

#define IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V_LSH      0
#define IPU_IC_CMBP_1_IC_PP_ALPHA_V_LSH         8

#define IPU_IC_CMBP_2_IC_KEY_COLOR_B_LSH        0
#define IPU_IC_CMBP_2_IC_KEY_COLOR_G_LSH        8
#define IPU_IC_CMBP_2_IC_KEY_COLOR_R_LSH        16

// PF_CONF
#define IPU_PF_CONF_PF_TYPE_LSH                 0
#define IPU_PF_CONF_H264_Y_PAUSE_EN_LSH         4
#define IPU_PF_CONF_H264_Y_PAUSE_ROW_LSH        16

// IDMAC_CONF
#define IPU_IDMAC_CONF_PRYM_LSH                 0
#define IPU_IDMAC_CONF_SRCNT_LSH                4
#define IPU_IDMAC_CONF_SINGLE_AHB_M_EN_LSH      8

// SDC_COM_CONF
#define IPU_SDC_COM_CONF_SDC_MODE_LSH           0
#define IPU_SDC_COM_CONF_BG_MCP_FROM_LSH        2
#define IPU_SDC_COM_CONF_FG_MCP_FROM_LSH        3
#define IPU_SDC_COM_CONF_FG_EN_LSH              4
#define IPU_SDC_COM_CONF_GWSEL_LSH              5
#define IPU_SDC_COM_CONF_SDC_GLB_LOC_A_LSH      6
#define IPU_SDC_COM_CONF_SDC_KEY_COLOR_EN_LSH   7
#define IPU_SDC_COM_CONF_MASK_EN_LSH            8
#define IPU_SDC_COM_CONF_BG_EN_LSH              9
#define IPU_SDC_COM_CONF_SHARP_LSH              12
#define IPU_SDC_COM_CONF_DUAL_MODE_LSH          15
#define IPU_SDC_COM_CONF_COC_LSH                16

// SDC_GRAPH_WIND_CTRL
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_B_LSH    0
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_G_LSH    8
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_R_LSH    16
#define IPU_SDC_GRAPH_WIND_CTRL_SDC_ALPHA_V_LSH        24

// SDC_FG_POS
#define IPU_SDC_FG_POS_FGYP_LSH                    0
#define IPU_SDC_FG_POS_FGXP_LSH                    16

// SDC_BG_POS
#define IPU_SDC_BG_POS_BGYP_LSH                    0
#define IPU_SDC_BG_POS_BGXP_LSH                    16

// SDC_CUR_POS
#define IPU_SDC_CUR_POS_CYP_LSH                    0
#define IPU_SDC_CUR_POS_CYH_LSH                    10
#define IPU_SDC_CUR_POS_CXP_LSH                    16
#define IPU_SDC_CUR_POS_CXW_LSH                    26

// SDC_CUR_BLINK_PWM_CTRL
#define IPU_SDC_CUR_BLINK_PWM_CTRL_BKDIV_LSH    0
#define IPU_SDC_CUR_BLINK_PWM_CTRL_BK_EN_LSH    15
#define IPU_SDC_CUR_BLINK_PWM_CTRL_PWM_LSH      16
#define IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN_LSH    24
#define IPU_SDC_CUR_BLINK_PWM_CTRL_SCR_LSH      25