📄 mxarm11_ipu.h
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//------------------------------------------------------------------------------
//
// Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// FREESCALE SEMICONDUCTOR, INC.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Header: mxarm11_ipu.h
//
// Provides definitions for IPU module based on Freescale ARM11 chassis.
//
//------------------------------------------------------------------------------
#ifndef __MXARM11_IPU_H
#define __MXARM11_IPU_H
#if __cplusplus
extern "C" {
#endif
//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
// Mutex to protect the integrity of the IPU common registers
#define IPU_COMMON_MUTEX TEXT("IPU_COMMON_REGISTERS")
//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
// IPU Common Registers
UINT32 IPU_CONF;
UINT32 IPU_CHA_BUF0_RDY;
UINT32 IPU_CHA_BUF1_RDY;
UINT32 IPU_CHA_DB_MODE_SEL;
UINT32 IPU_CHA_CUR_BUF;
UINT32 IPU_FS_PROC_FLOW;
UINT32 IPU_FS_DISP_FLOW;
UINT32 IPU_TASK_STAT;
UINT32 IPU_IMA_ADDR;
UINT32 IPU_IMA_DATA;
UINT32 IPU_INT_CTRL_1;
UINT32 IPU_INT_CTRL_2;
UINT32 IPU_INT_CTRL_3;
UINT32 IPU_INT_CTRL_4;
UINT32 IPU_INT_CTRL_5;
UINT32 IPU_INT_STAT_1;
UINT32 IPU_INT_STAT_2;
UINT32 IPU_INT_STAT_3;
UINT32 IPU_INT_STAT_4;
UINT32 IPU_INT_STAT_5;
UINT32 IPU_BRK_CTRL_1;
UINT32 IPU_BRK_CTRL_2;
UINT32 IPU_BRK_STAT;
UINT32 IPU_DIAGB_CTRL;
// IPU CSI Registers
UINT32 CSI_SENS_CONF;
UINT32 CSI_SENS_FRM_SIZE;
UINT32 CSI_ACT_FRM_SIZE;
UINT32 CSI_OUT_FRM_CTRL;
UINT32 CSI_TST_CTRL;
UINT32 CSI_CCIR_CODE_1;
UINT32 CSI_CCIR_CODE_2;
UINT32 CSI_CCIR_CODE_3;
UINT32 CSI_FLASH_STROBE_1;
UINT32 CSI_FLASH_STROBE_2;
// IPU IC Registers
UINT32 IC_CONF;
UINT32 IC_PRP_ENC_RSC;
UINT32 IC_PRP_VF_RSC;
UINT32 IC_PP_RSC;
UINT32 IC_CMBP_1;
UINT32 IC_CMBP_2;
// IPU PF Registers
UINT32 PF_CONF;
// IPU IDMAC Registers
UINT32 IDMAC_CONF;
UINT32 IDMAC_CHA_EN;
UINT32 IDMAC_CHA_PRI;
UINT32 IDMAC_CHA_BUSY;
// IPU SDC (Synchronous Display Controller) Registers
UINT32 SDC_COM_CONF;
UINT32 SDC_GRAPH_WIND_CTRL;
UINT32 SDC_FG_POS;
UINT32 SDC_BG_POS;
UINT32 SDC_CUR_POS;
UINT32 SDC_CUR_BLINK_PWM_CTRL;
UINT32 SDC_CUR_MAP;
UINT32 SDC_HOR_CONF;
UINT32 SDC_VER_CONF;
UINT32 SDC_SHARP_CONF_1;
UINT32 SDC_SHARP_CONF_2;
// IPU ADC (Asynchronous Display Controller) Registers
UINT32 ADC_CONF;
UINT32 ADC_SYSCHA1_SA;
UINT32 ADC_SYSCHA2_SA;
UINT32 ADC_PRPCHAN_SA;
UINT32 ADC_PPCHAN_SA;
UINT32 ADC_DISP0_CONF;
UINT32 ADC_DISP0_RD_AP;
UINT32 ADC_DISP0_RDM;
UINT32 ADC_DISP0_SS;
UINT32 ADC_DISP1_CONF;
UINT32 ADC_DISP1_RD_AP;
UINT32 ADC_DISP1_RDM;
UINT32 ADC_DISP12_SS;
UINT32 ADC_DISP2_CONF;
UINT32 ADC_DISP2_RD_AP;
UINT32 ADC_DISP2_RDM;
UINT32 ADC_DISP_VSYNC;
// IPU DI Registers
UINT32 DI_DISP_IF_CONF;
UINT32 DI_DISP_SIG_POL;
UINT32 DI_SER_DISP1_CONF;
UINT32 DI_SER_DISP2_CONF;
UINT32 DI_HSP_CLK_PER;
UINT32 DI_DISP0_TIME_CONF_1;
UINT32 DI_DISP0_TIME_CONF_2;
UINT32 DI_DISP0_TIME_CONF_3;
UINT32 DI_DISP1_TIME_CONF_1;
UINT32 DI_DISP1_TIME_CONF_2;
UINT32 DI_DISP1_TIME_CONF_3;
UINT32 DI_DISP2_TIME_CONF_1;
UINT32 DI_DISP2_TIME_CONF_2;
UINT32 DI_DISP2_TIME_CONF_3;
UINT32 DI_DISP3_TIME_CONF;
UINT32 DI_DISP0_DB0_MAP;
UINT32 DI_DISP0_DB1_MAP;
UINT32 DI_DISP0_DB2_MAP;
UINT32 DI_DISP0_CB0_MAP;
UINT32 DI_DISP0_CB1_MAP;
UINT32 DI_DISP0_CB2_MAP;
UINT32 DI_DISP1_DB0_MAP;
UINT32 DI_DISP1_DB1_MAP;
UINT32 DI_DISP1_DB2_MAP;
UINT32 DI_DISP1_CB0_MAP;
UINT32 DI_DISP1_CB1_MAP;
UINT32 DI_DISP1_CB2_MAP;
UINT32 DI_DISP2_DB0_MAP;
UINT32 DI_DISP2_DB1_MAP;
UINT32 DI_DISP2_DB2_MAP;
UINT32 DI_DISP2_CB0_MAP;
UINT32 DI_DISP2_CB1_MAP;
UINT32 DI_DISP2_CB2_MAP;
UINT32 DI_DISP3_B0_MAP;
UINT32 DI_DISP3_B1_MAP;
UINT32 DI_DISP3_B2_MAP;
UINT32 DI_DISP_ACC_CC;
UINT32 DI_DISP_LLA_CONF;
UINT32 DI_DISP_LLA_DATA;
} CSP_IPU_REGS, *PCSP_IPU_REGS;
//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
// IPU Common Registers
#define IPU_IPU_CONF_OFFSET 0x0000
#define IPU_IPU_CHA_BUF0_RDY_OFFSET 0x0004
#define IPU_IPU_CHA_BUF1_RDY_OFFSET 0x0008
#define IPU_IPU_CHA_DB_MODE_SEL_OFFSET 0x000C
#define IPU_IPU_CHA_CUR_BUF_OFFSET 0x0010
#define IPU_IPU_FS_PROC_FLOW_OFFSET 0x0014
#define IPU_IPU_FS_DISP_FLOW_OFFSET 0x0018
#define IPU_IPU_TASK_STAT_OFFSET 0x001C
#define IPU_IPU_IMA_ADDR_OFFSET 0x0020
#define IPU_IPU_IMA_DATA_OFFSET 0x0024
#define IPU_IPU_INT_CTRL_1_OFFSET 0x0028
#define IPU_IPU_INT_CTRL_2_OFFSET 0x002C
#define IPU_IPU_INT_CTRL_3_OFFSET 0x0030
#define IPU_IPU_INT_CTRL_4_OFFSET 0x0034
#define IPU_IPU_INT_CTRL_5_OFFSET 0x0038
#define IPU_IPU_INT_STAT_1_OFFSET 0x003C
#define IPU_IPU_INT_STAT_2_OFFSET 0x0040
#define IPU_IPU_INT_STAT_3_OFFSET 0x0044
#define IPU_IPU_INT_STAT_4_OFFSET 0x0048
#define IPU_IPU_INT_STAT_5_OFFSET 0x004C
#define IPU_IPU_BRK_CTRL_1_OFFSET 0x0050
#define IPU_IPU_BRK_CTRL_2_OFFSET 0x0054
#define IPU_IPU_BRK_STAT_OFFSET 0x0058
#define IPU_IPU_DIAGB_CTRL_OFFSET 0x005C
// IPU CSI Registers
#define IPU_CSI_SENS_CONF_OFFSET 0x0060
#define IPU_CSI_SENS_FRM_SIZE_OFFSET 0x0064
#define IPU_CSI_ACT_FRM_SIZE_OFFSET 0x0068
#define IPU_CSI_OUT_FRM_CTRL_OFFSET 0x006C
#define IPU_CSI_TST_CTRL_OFFSET 0x0070
#define IPU_CSI_CCIR_CODE_1_OFFSET 0x0074
#define IPU_CSI_CCIR_CODE_2_OFFSET 0x0078
#define IPU_CSI_CCIR_CODE_3_OFFSET 0x007C
#define CSI_FLASH_STROBE_1_OFFSET 0x0080
#define CSI_FLASH_STROBE_2_OFFSET 0x0084
// IPU IC Registers
#define IPU_IC_CONF_OFFSET 0x0088
#define IPU_IC_PRP_ENC_RSC_OFFSET 0x008C
#define IPU_IC_PRP_VF_RSC_OFFSET 0x0090
#define IPU_IC_PP_RSC_OFFSET 0x0094
#define IPU_IC_CMBP_1_OFFSET 0x0098
#define IPU_IC_CMBP_2_OFFSET 0x009C
// IPU PF Registers
#define IPU_PF_CONF_OFFSET 0x00A0
// IPU IDMAC Registers
#define IPU_IDMAC_CONF_OFFSET 0x00A4
#define IPU_IDMAC_CHA_EN_OFFSET 0x00A8
#define IPU_IDMAC_CHA_PRI_OFFSET 0x00AC
#define IPU_IDMAC_CHA_BUSY_OFFSET 0x00B0
// IPU SDC Synchronous Display Controller) Registers
#define IPU_SDC_COM_CONF_OFFSET 0x00B4
#define IPU_SDC_GRAPH_WIND_CTRL_OFFSET 0x00B8
#define IPU_SDC_FG_POS_OFFSET 0x00BC
#define IPU_SDC_BG_POS_OFFSET 0x00C0
#define IPU_SDC_CUR_POS_OFFSET 0x00C4
#define IPU_SDC_CUR_BLINK_PWM_CTRL_OFFSET 0x00C8
#define IPU_SDC_CUR_MAP_OFFSET 0x00CC
#define IPU_SDC_HOR_CONF_OFFSET 0x00D0
#define IPU_SDC_VER_CONF_OFFSET 0x00D4
#define IPU_SDC_SHARP_CONF_1_OFFSET 0x00D8
#define IPU_SDC_SHARP_CONF_2_OFFSET 0x00DC
// IPU ADC (Asynchronous Display Controller) Registers
#define IPU_ADC_CONF_OFFSET 0x00E0
#define IPU_ADC_SYSCHA1_SA_OFFSET 0x00E4
#define IPU_ADC_SYSCHA2_SA_OFFSET 0x00E8
#define IPU_ADC_PRPCHAN_SA_OFFSET 0x00EC
#define IPU_ADC_PPCHAN_SA_OFFSET 0x00F0
#define IPU_ADC_DISP0_CONF_OFFSET 0x00F4
#define IPU_ADC_DISP0_RD_AP_OFFSET 0x00F8
#define IPU_ADC_DISP0_RDM_OFFSET 0x00FC
#define IPU_ADC_DISP0_SS_OFFSET 0x0100
#define IPU_ADC_DISP1_CONF_OFFSET 0x0104
#define IPU_ADC_DISP1_RD_AP_OFFSET 0x0108
#define IPU_ADC_DISP1_RDM_OFFSET 0x010C
#define IPU_ADC_DISP12_SS_OFFSET 0x0110
#define IPU_ADC_DISP2_CONF_OFFSET 0x0114
#define IPU_ADC_DISP2_RD_AP_OFFSET 0x0118
#define IPU_ADC_DISP2_RDM_OFFSET 0x011C
#define IPU_ADC_DISP2_SS_OFFSET 0x0120
// IPU DI Registers
#define IPU_DI_DISP_IF_CONF_OFFSET 0x0124
#define IPU_DI_DISP_SIG_POL_OFFSET 0x0128
#define IPU_DI_SER_DISP1_CONF_OFFSET 0x012C
#define IPU_DI_SER_DISP2_CONF_OFFSET 0x0130
#define IPU_DI_HSP_CLK_PER_OFFSET 0x0134
#define IPU_DI_DISP0_TIME_CONF_1_OFFSET 0x0138
#define IPU_DI_DISP0_TIME_CONF_2_OFFSET 0x013C
#define IPU_DI_DISP0_TIME_CONF_3_OFFSET 0x0140
#define IPU_DI_DISP1_TIME_CONF_1_OFFSET 0x0144
#define IPU_DI_DISP1_TIME_CONF_2_OFFSET 0x0148
#define IPU_DI_DISP1_TIME_CONF_3_OFFSET 0x014C
#define IPU_DI_DISP2_TIME_CONF_1_OFFSET 0x0150
#define IPU_DI_DISP2_TIME_CONF_2_OFFSET 0x0154
#define IPU_DI_DISP2_TIME_CONF_3_OFFSET 0x0158
#define IPU_DI_DISP3_TIME_CONF_OFFSET 0x015C
#define IPU_DI_DISP0_DB0_MAP_OFFSET 0x0160
#define IPU_DI_DISP0_DB1_MAP_OFFSET 0x0164
#define IPU_DI_DISP0_DB2_MAP_OFFSET 0x0168
#define IPU_DI_DISP0_CB0_MAP_OFFSET 0x016C
#define IPU_DI_DISP0_CB1_MAP_OFFSET 0x0170
#define IPU_DI_DISP0_CB2_MAP_OFFSET 0x0174
#define IPU_DI_DISP1_DB0_MAP_OFFSET 0x0178
#define IPU_DI_DISP1_DB1_MAP_OFFSET 0x017C
#define IPU_DI_DISP1_DB2_MAP_OFFSET 0x0180
#define IPU_DI_DISP1_CB0_MAP_OFFSET 0x0184
#define IPU_DI_DISP1_CB1_MAP_OFFSET 0x0188
#define IPU_DI_DISP1_CB2_MAP_OFFSET 0x018C
#define IPU_DI_DISP2_DB0_MAP_OFFSET 0x0190
#define IPU_DI_DISP2_DB1_MAP_OFFSET 0x0194
#define IPU_DI_DISP2_DB2_MAP_OFFSET 0x0198
#define IPU_DI_DISP2_CB0_MAP_OFFSET 0x019C
#define IPU_DI_DISP2_CB1_MAP_OFFSET 0x01A0
#define IPU_DI_DISP2_CB2_MAP_OFFSET 0x01A4
#define IPU_DI_DISP3_B0_MAP_OFFSET 0x01A8
#define IPU_DI_DISP3_B1_MAP_OFFSET 0x01AC
#define IPU_DI_DISP3_B2_MAP_OFFSET 0x01B0
#define IPU_DI_DISP_ACC_CC_OFFSET 0x01B4
#define IPU_DI_DISP_LLA_CONF_OFFSET 0x01B8
#define IPU_DI_DISP_LLA_DATA_OFFSET 0x01BC
//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
// IPU_CONF
#define IPU_IPU_CONF_CSI_EN_LSH 0
#define IPU_IPU_CONF_IC_EN_LSH 1
#define IPU_IPU_CONF_ROT_EN_LSH 2
#define IPU_IPU_CONF_PF_EN_LSH 3
#define IPU_IPU_CONF_SDC_EN_LSH 4
#define IPU_IPU_CONF_ADC_EN_LSH 5
#define IPU_IPU_CONF_DI_EN_LSH 6
#define IPU_IPU_CONF_DU_EN_LSH 7
#define IPU_IPU_CONF_PXL_ENDIAN_LSH 8
// IPU DMA Channel ID used in the various IPU registers
#define IPU_DMA_CHA_DMAIC_0_LSH 0
#define IPU_DMA_CHA_DMAIC_1_LSH 1
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