mx31_ccm.h

freescale i.mx31 BSP CE5.0全部源码

//------------------------------------------------------------------------------
//
//  Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  FREESCALE SEMICONDUCTOR, INC.
//
//------------------------------------------------------------------------------
//
//  Header:  mx31_ccm.h
//
//  Provides the public interface for the CCM module.  This module defines
//  the header information for the application processor's clock and reset
//  module.
//
//------------------------------------------------------------------------------

#ifndef __MX31_CCM_H__
#define __MX31_CCM_H__

#ifdef __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
#define CCM_CGR_CG_MASK                 (0x3)

//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
    UINT32 CCMR;
    UINT32 PDR0;
    UINT32 PDR1;
    UINT32 RCSR;
    UINT32 MPCTL;
    UINT32 UPCTL;
    UINT32 SRPCTL;
    UINT32 COSR;
    UINT32 CGR[3];
    UINT32 WIMR;
    UINT32 LDC;
    UINT32 DCVR[4];
    UINT32 LTR0;
    UINT32 LTR1;
    UINT32 LTR2;
    UINT32 LTR3;
    UINT32 LTBR0;
    UINT32 LTBR1;
    UINT32 PMCR0;
    UINT32 PMCR1;
    UINT32 PDR;  
} CSP_CCM_REGS, *PCSP_CCM_REGS;

//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
#define CCM_CCMR_OFFSET                 0x0000
#define CCM_PDR0_OFFSET                 0x0004
#define CCM_PDR1_OFFSET                 0x0008
#define CCM_RCSR_OFFSET                 0x000C
#define CCM_MPCTL_OFFSET                0x0010
#define CCM_UPCTL_OFFSET                0x0014
#define CCM_SRPCTL_OFFSET               0x0018
#define CCM_COSR_OFFSET                 0x001C
#define CCM_CGR_OFFSET                  0x0020
#define CCM_WIMR_OFFSET                 0x002C
#define CCM_LDC_OFFSET                  0x0030
#define CCM_DCVR_OFFSET                 0x0034
#define CCM_LTR0_OFFSET                 0x0044
#define CCM_LTR1_OFFSET                 0x0048
#define CCM_LTR2_OFFSET                 0x004C
#define CCM_LTR3_OFFSET                 0x0050
#define CCM_LTBR0_OFFSET                0x0054
#define CCM_LTBR1_OFFSET                0x0058
#define CCM_PMCR0_OFFSET                0x005C
#define CCM_PMCR1_OFFSET                0x0060
#define CCM_PDR_OFFSET                  0x0064


//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define CCM_CCMR_FPME_LSH               0
#define CCM_CCMR_PRCS_LSH               1
#define CCM_CCMR_MPE_LSH                3
#define CCM_CCMR_SBYCS_LSH              4
#define CCM_CCMR_MDS_LSH                7
#define CCM_CCMR_SPE_LSH                8
#define CCM_CCMR_UPE_LSH                9
#define CCM_CCMR_FIRS_LSH               11
#define CCM_CCMR_LPM_LSH                14
#define CCM_CCMR_SSI1S_LSH              18
#define CCM_CCMR_SSI2S_LSH              21
#define CCM_CCMR_PERCS_LSH              24
#define CCM_CCMR_CSCS_LSH               25
#define CCM_CCMR_FPMF_LSH               26
#define CCM_CCMR_WBEN_LSH               27
#define CCM_CCMR_VSTBY_LSH              28
#define CCM_CCMR_L2PG_LSH               29

#define CCM_PDR0_MCU_PODF_LSH           0
#define CCM_PDR0_MAX_PODF_LSH           3
#define CCM_PDR0_IPG_PODF_LSH           6
#define CCM_PDR0_NFC_PODF_LSH           8
#define CCM_PDR0_HSP_PODF_LSH           11
#define CCM_PDR0_PER_PODF_LSH           16
#define CCM_PDR0_CSI_PODF_LSH           23

#define CCM_PDR1_SSI1_PODF_LSH          0
#define CCM_PDR1_SSI1_PRE_PODF_LSH      6
#define CCM_PDR1_SSI2_PODF_LSH          9
#define CCM_PDR1_SSI2_PRE_PODF_LSH      15
#define CCM_PDR1_FIRI_PODF_LSH          18
#define CCM_PDR1_FIRI_PRE_PODF_LSH      24
#define CCM_PDR1_USB_PODF_LSH           27
#define CCM_PDR1_USB_PRDF_LSH           30

#define CCM_RCSR_REST_LSH               0
#define CCM_RCSR_GPF_LSH                4
#define CCM_RCSR_SDM_LSH                12
#define CCM_RCSR_MPRES_LSH              15
#define CCM_RCSR_OSCNT_LSH              16
#define CCM_RCSR_BTP_LSH                23
#define CCM_RCSR_NFMS_LSH               30
#define CCM_RCSR_NF16B_LSH              31

#define CCM_MPCTL_MFN_LSH               0
#define CCM_MPCTL_MFI_LSH               10
#define CCM_MPCTL_MFD_LSH               16
#define CCM_MPCTL_PDF_LSH               26
#define CCM_MPCTL_BRMO_LSH              31

#define CCM_UPCTL_MFN_LSH               0
#define CCM_UPCTL_MFI_LSH               10
#define CCM_UPCTL_MFD_LSH               16
#define CCM_UPCTL_PDF_LSH               26
#define CCM_UPCTL_BRMO_LSH              31

#define CCM_SPCTL_MFN_LSH               0
#define CCM_SPCTL_MFI_LSH               10
#define CCM_SPCTL_MFD_LSH               16
#define CCM_SPCTL_PDF_LSH               26
#define CCM_SPCTL_BRMO_LSH              31

#define CCM_COSR_CLKOSEL_LSH            0
#define CCM_COSR_CLKODIV_LSH            6
#define CCM_COSR_CLKOEN_LSH             9

#define CCM_DCVR_ELV_LSH                2
#define CCM_DCVR_LLV_LSH                12
#define CCM_DCVR_ULV_LSH                22

#define CCM_LTR0_DIV3CK_LSH             1
#define CCM_LTR0_SIGD0_LSH              3
#define CCM_LTR0_DNTHR_LSH              16
#define CCM_LTR0_UPTHR_LSH              22
#define CCM_LTR0_SIGD13_LSH             29

#define CCM_LTR1_PNCTHR_LSH             0
#define CCM_LTR1_UPCNT_LSH              6
#define CCM_LTR1_DNCNT_LSH              14
#define CCM_LTR1_LTBRSR_LSH             22
#define CCM_LTR1_LTBRSH_LSH             23

#define CCM_LTR2_EMAC_LSH               0
#define CCM_LTR2_WSW9_LSH               9

#define CCM_LTR3_WSW0_LSH               5

#define CCM_PMCR0_DPTEN_LSH             0
#define CCM_PMCR0_PTVAI_LSH             1
#define CCM_PMCR0_PTVAIM_LSH            3
#define CCM_PMCR0_DVFEN_LSH             4
#define CCM_PMCR0_DCR_LSH               5
#define CCM_PMCR0_DRCE0_LSH             6
#define CCM_PMCR0_DRCE1_LSH             7
#define CCM_PMCR0_DRCE2_LSH             8
#define CCM_PMCR0_DRCE3_LSH             9
#define CCM_PMCR0_WFIM_LSH              10
#define CCM_PMCR0_DPVV_LSH              11
#define CCM_PMCR0_DPVCR_LSH             12
#define CCM_PMCR0_FSVAI_LSH             13
#define CCM_PMCR0_FSVAIM_LSH            15
#define CCM_PMCR0_UPDTEN_LSH            16
#define CCM_PMCR0_PTVIS_LSH             17
#define CCM_PMCR0_LBCF_LSH              18
#define CCM_PMCR0_LBFL_LSH              20
#define CCM_PMCR0_LBMI_LSH              21
#define CCM_PMCR0_DVFIS_LSH             22
#define CCM_PMCR0_DVFEV_LSH             23
#define CCM_PMCR0_VSCNT_LSH             24
#define CCM_PMCR0_UDSC_LSH              27
#define CCM_PMCR0_DVSUP_LSH             28
#define CCM_PMCR0_DVS1_LSH              28
#define CCM_PMCR0_DVS0_LSH              29
#define CCM_PMCR0_DFSUP0_LSH            30
#define CCM_PMCR0_DFSUP1_LSH            31

#define CCM_PMCR1_DVGP_LSH              0
#define CCM_PMCR1_CPFA_LSH              6
#define CCM_PMCR1_NWTS_LSH              7
#define CCM_PMCR1_PWTS_LSH              8
#define CCM_PMCR1_CPSPA_LSH             9
#define CCM_PMCR1_WBCN_LSH              16

//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define CCM_CCMR_FPME_WID               1
#define CCM_CCMR_PRCS_WID               2
#define CCM_CCMR_MPE_WID                1
#define CCM_CCMR_SBYCS_WID              1
#define CCM_CCMR_MDS_WID                1
#define CCM_CCMR_SPE_WID                1
#define CCM_CCMR_UPE_WID                1
#define CCM_CCMR_FIRS_WID               2
#define CCM_CCMR_LPM_WID                2
#define CCM_CCMR_SSI1S_WID              2
#define CCM_CCMR_SSI2S_WID              2
#define CCM_CCMR_PERCS_WID              1
#define CCM_CCMR_CSCS_WID               1
#define CCM_CCMR_FPMF_WID               1
#define CCM_CCMR_WBEN_WID               1
#define CCM_CCMR_VSTBY_WID              1
#define CCM_CCMR_L2PG_WID               1

#define CCM_PDR0_MCU_PODF_WID           3
#define CCM_PDR0_MAX_PODF_WID           3
#define CCM_PDR0_IPG_PODF_WID           2
#define CCM_PDR0_NFC_PODF_WID           3
#define CCM_PDR0_HSP_PODF_WID           3
#define CCM_PDR0_PER_PODF_WID           5
#define CCM_PDR0_CSI_PODF_WID           9

#define CCM_PDR1_SSI1_PODF_WID          6
#define CCM_PDR1_SSI1_PRE_PODF_WID      3
#define CCM_PDR1_SSI2_PODF_WID          6
#define CCM_PDR1_SSI2_PRE_PODF_WID      3
#define CCM_PDR1_FIRI_PODF_WID          6
#define CCM_PDR1_FIRI_PRE_PODF_WID      3
#define CCM_PDR1_USB_PODF_WID           3
#define CCM_PDR1_USB_PRDF_WID           2

#define CCM_RCSR_REST_WID               3
#define CCM_RCSR_GPF_WID                4
#define CCM_RCSR_SDM_WID                2
#define CCM_RCSR_MPRES_WID              1
#define CCM_RCSR_OSCNT_WID              7
#define CCM_RCSR_BTP_WID                5
#define CCM_RCSR_NFMS_WID               1
#define CCM_RCSR_NF16B_WID              1

#define CCM_MPCTL_MFN_WID               10
#define CCM_MPCTL_MFI_WID               4
#define CCM_MPCTL_MFD_WID               10
#define CCM_MPCTL_PDF_WID               4
#define CCM_MPCTL_BRMO_WID              1

#define CCM_UPCTL_MFN_WID               10
#define CCM_UPCTL_MFI_WID               4
#define CCM_UPCTL_MFD_WID               10