mx31_usb.h

freescale i.mx31 BSP CE5.0全部源码

//------------------------------------------------------------------------------
//
// Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// Freescale Semiconductor, Inc.
//
//------------------------------------------------------------------------------
//
//  Header:  mx31_usb.h
//
//  Provides definitions for usb module based on Freescale MX31 SoC.
//
//------------------------------------------------------------------------------
#ifndef __MX31_USB_H
#define __MX31_USB_H


#if __cplusplus
extern "C" {
#endif

typedef struct {        
    //****************OTG Registers **********************************************
                                //      off DEV OTG SPH MPH 
    UINT32 ID;                  // RO   0   *   *   *   *   Identification Register
    UINT32 HWGENERAL;           // RO   4   *   *   *   *   General Hardware Parameters
    UINT32 HWHOST;              // RO   8       *   *   *   Host Hardware Parameters    
    UINT32 HWDEVICE;            // RO   C   *   *           Device Hardware Parameters
    UINT32 HWTXBUF;         // RO   0x10    *   *   *   *   TX Buffer Hardware Parameters       
    UINT32 HWRXBUF;         // RO   0x14    *   *   *   *   RX Buffer Hardware Parameters 
    UINT32 HWTTTXBUF;           //      0x18                *   TT-TX Buffer Hardware Parameters
    UINT32 HWTTRXBUF;           //      0x1C                *   TT-RX Buffer Hardware Parameters
    UINT32 RESERVED1[56];       //      0x20-0xfc       
    UINT8   CAPLENGTH;          // RO   0x100*  *   *   *   Capability Register Length
    UINT8   RESERVED2;          //      0x101
    UINT16 HCIVERSION;          // RO   0x102   *   *   *   Host Interface Version Number
    UINT32 HCSPARAMS;           // RO   0x104   *   *   *   Host Control Structural Parameters
    UINT32 HCCPARAMS;           // RO   0x108   *   *   *   Host Control Capability Parameters
    UINT32 RESERVED3[5];        //      0x10C-0x11f
    UINT16 DCIVERSION;          // RO   0x120*  *           Device Interface Version Number
    UINT16 RESERVED4;           //      0x122
    UINT32 DCCPARAMS;           // RO   0x124*  *           Device Control CapabilityParameters
    UINT32 RESERVED5[6];        //      0x128-0x13C
    UINT32 USBCMD;              //      0x140*  *   *   *   USB Command
    UINT32 USBSTS;              //      0x144*  *   *   *   USB Status
    UINT32 USBINTR;             //      0x148*  *   *   *   USB Interrupt Enable
    UINT32 FRINDEX;             //      0x14C*  *   *   *   USB Frame Index; Read/Write in host mode, Read in device mode
    UINT32 CTRLDSSENGMENT;  // RO   0x150               This register is not used in this implementation.
    union {
        UINT32 PERIODICLISTBASE;//      0x154   *   *   *   Frame List Base Address
        UINT32 USBADR;          //          *   *           USB Device Address
    }T_154H;                    // Read/Write (Writes must be DWord Writes)
    union {
        UINT32 ASYNCLISTADDR;   //      0x158   *   *   *   Next Asynchronous List Address
        UINT32 ENDPOINTLISTADDR;//          *   *           Address at Endpoint list in memory
    }T_158H;                        // Read/Write (Writes must be DWord Writes)
    UINT32 ASYNCTTSTS;          // 0x15C            *   Asynchronous Buffer Status For Embedded TT.
    UINT32 BURSTSIZE;           //      0x160*  *   *   *   Programmable Burst Size.
    UINT32 TXFILLTUNING;        //      0x164   *   *   *   Host Transmit Pre-Buffer Packet Tuning
    UINT32 TXTTFILLTUNING;      // 0x168                *   Host TT Transmit Pre-Buffer Packet Tuning
    UINT32 RESERVED7;           //      0x16C
    UINT32 ULPI_VIEWPORT;       //      0x170
    UINT32 RESERVED8[3];        //      0x174-0x17C
    UINT32 CONFIGFLAG;          // RO   0x180   *   *   *   Configured Flag Register, This register is not used in this implementation. A read from this register returns a constant of a 00000001h to indicate that all port routings default to this host controller.
    UINT32 PORTSC[8];           //      0x184-0x1A0             
                                //          *   *   *   *   Port Status/Control X
    UINT32 OTGSC;               //      0x1A4   *           On-The-Go(OTG) Status and Control
    UINT32 USBMODE;         //      0x1A8*  *   *   *   USB Device Mode
    UINT32 ENDPTSETUPSTAT;      //      0x1AC*  *           Endpoint Setup Status
    UINT32 ENDPTPRIME;          //      0x1B0*  *           Endpoint Initialization
    UINT32 ENDPTFLUSH;          //      0x1B4*  *           Endpoint De-Initialize
    UINT32 ENDPTSTATUS;     //      0x1B8*  *           Endpoint Status
    UINT32 ENDPTCOMPLETE;       //      0x1BC*  *           Endpoint Complete
    UINT32 ENDPTCTRL0;          //      0x1C0*  *           Endpoint Control 0
    UINT32 ENDPTCTRL    [15];   //      0x1C4-0x1FC 
                                //          *   *           Endpoint Control 1-15
                                
} CSP_USB_REG, * PCSP_USB_REG;

typedef volatile struct {       
    CSP_USB_REG OTG;                    //  0
    CSP_USB_REG H1;                 //  0x200
    CSP_USB_REG H2;                 //  0x400
    UINT32       USB_CTRL;              //    0x600
    UINT32       USB_OTG_MIRROR;        //    0x604
} CSP_USB_REGS, * PCSP_USB_REGS;

typedef struct _USB_ID {
    unsigned int ID:8;          // Configuration number. This number is set to 0x05 
                            //and indicates that the peripheral is the ARC USB-HS OTG
                            //High-Speed USB On-The-Go USB 2.0 core.
    unsigned int NID:8;     // Ones complement version of ID[5:0].
    unsigned int REVISION:8;    // Revision number of the core
    unsigned int RESERVED:8;    // These bits are reserved and should be set to zero
} USB_ID_T;

typedef struct _USB_HWGENERAL {
    unsigned int RT:1;          // VUSB_HS_RESET_TYPE
    unsigned int CLKC:2;        // VUSB_HS_CLOCK_CONFIGURATION
    unsigned int BWT:1;     // Reserved for internal testing.
    unsigned int PHYW:2;        // VUSB_HS_PHY16_8
    unsigned int PHYM:3;        // VUSB_HS_PHY_TYPE
    unsigned int SM:1;          // VUSB_HS_PHY_SERIAL
    unsigned int RESERVED:22;   // Reserved. These bits are reserved and should be set to zero.
} USB_HWGENERAL_T;

typedef struct _USB_HWHOST {
    unsigned int HC:1;          // VUSB_HS_HOST
    unsigned int NPORT:3;       // VUSB_HS_NUM_PORT-1
    unsigned int RESERVED:12;   // Reserved. These bits are reserved and should be set to zero.
    unsigned int TTASY:8;       // VUSB_HS_TT_ASYNC_CONTEXTS
    unsigned int TTPER:8;       // VUSB_HS_TT_PERIODIC_CONTEXTS
} USB_HWHOST_T;

typedef struct _USB_HWDEVICE {
    unsigned int DC:1;          // device capable; [VUSB_HS_DEV /= 0]
    unsigned int DEVEP:5;       // VUSB_HS_DEV_EP
    unsigned int RESERVED:26;   // Reserved. These bits are reserved and should be set to zero.
} USB_HWDEVICE_T;

typedef struct _USB_HWTXBUF {
    unsigned int TCBURST:8; // VUSB_HS_TX_BURST
    unsigned int TXADD:8;   // VUSB_HS_TX_ADD
    unsigned int TXCHANADD:8;   // VUSB_HS_TX_CHAN_ADD
    unsigned int TXLC:1;        // VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS
}USB_HWTXBUF_T;


typedef struct _USB_HWRXBUF {
    unsigned int RXBURST:8; // VUSB_HS_RX_BURST
    unsigned int RXADD:8;       // VUSB_HS_RX_ADD
    unsigned int RESERVED:16;   // Reserved. These bits are reserved and should be set to zero.
}USB_HWRXBUF_T;

typedef struct _USB_HCSPARAMS { //Port steering logic capabilities are described in this register.