📄 mx31_ddk.h
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//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// Freescale Semiconductor, Inc.
//
//------------------------------------------------------------------------------
//
// File: mx31_ddk.h
//
// Contains MX31 definitions to assist with driver development.
//
//------------------------------------------------------------------------------
#ifndef __MX31_DDK_H
#define __MX31_DDK_H
//------------------------------------------------------------------------------
// Types
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_SIGNAL
//
// Clock signal name for querying/setting clock configuration.
//
//-----------------------------------------------------------------------------
typedef enum
{
DDK_CLOCK_SIGNAL_MCUPLL = 0,
DDK_CLOCK_SIGNAL_USBPLL = 1,
DDK_CLOCK_SIGNAL_SERPLL = 2,
DDK_CLOCK_SIGNAL_ARM = 3,
DDK_CLOCK_SIGNAL_IPU = 4,
DDK_CLOCK_SIGNAL_AHB = 5,
DDK_CLOCK_SIGNAL_IPG = 6,
DDK_CLOCK_SIGNAL_NFC = 7,
DDK_CLOCK_SIGNAL_GACC = 8,
DDK_CLOCK_SIGNAL_SSI1 = 9,
DDK_CLOCK_SIGNAL_SSI2 = 10,
DDK_CLOCK_SIGNAL_FIRI = 11,
DDK_CLOCK_SIGNAL_CSI = 12,
DDK_CLOCK_SIGNAL_USB = 13,
DDK_CLOCK_SIGNAL_SIM = 14,
DDK_CLOCK_SIGNAL_PER = 15,
DDK_CLOCK_SIGNAL_ENUM_END = 16
} DDK_CLOCK_SIGNAL;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_GATE_INDEX
//
// Index for referencing the corresponding clock gating control bits within
// the CCM.
//
//-----------------------------------------------------------------------------
typedef enum
{
DDK_CLOCK_GATE_INDEX_SDHC1 = 0,
DDK_CLOCK_GATE_INDEX_SDHC2 = 1,
DDK_CLOCK_GATE_INDEX_GPT = 2,
DDK_CLOCK_GATE_INDEX_EPIT1 = 3,
DDK_CLOCK_GATE_INDEX_EPIT2 = 4,
DDK_CLOCK_GATE_INDEX_IIM = 5,
DDK_CLOCK_GATE_INDEX_ATA = 6,
DDK_CLOCK_GATE_INDEX_SDMA = 7,
DDK_CLOCK_GATE_INDEX_CSPI3 = 8,
DDK_CLOCK_GATE_INDEX_RNG = 9,
DDK_CLOCK_GATE_INDEX_UART1 = 10,
DDK_CLOCK_GATE_INDEX_UART2 = 11,
DDK_CLOCK_GATE_INDEX_SSI1 = 12,
DDK_CLOCK_GATE_INDEX_I2C1 = 13,
DDK_CLOCK_GATE_INDEX_I2C2 = 14,
DDK_CLOCK_GATE_INDEX_I2C3 = 15,
DDK_CLOCK_GATE_INDEX_MPEG4 = 16,
DDK_CLOCK_GATE_INDEX_MEMSTICK1 = 17,
DDK_CLOCK_GATE_INDEX_MEMSTICK2 = 18,
DDK_CLOCK_GATE_INDEX_CSI = 19,
DDK_CLOCK_GATE_INDEX_RTC = 20,
DDK_CLOCK_GATE_INDEX_WDOG = 21,
DDK_CLOCK_GATE_INDEX_PWM = 22,
DDK_CLOCK_GATE_INDEX_SIM = 23,
DDK_CLOCK_GATE_INDEX_ECT = 24,
DDK_CLOCK_GATE_INDEX_USBOTG = 25,
DDK_CLOCK_GATE_INDEX_KPP = 26,
DDK_CLOCK_GATE_INDEX_IPU = 27,
DDK_CLOCK_GATE_INDEX_UART3 = 28,
DDK_CLOCK_GATE_INDEX_UART4 = 29,
DDK_CLOCK_GATE_INDEX_UART5 = 30,
DDK_CLOCK_GATE_INDEX_OWIRE = 31,
DDK_CLOCK_GATE_INDEX_SSI2 = 32,
DDK_CLOCK_GATE_INDEX_CSPI1 = 33,
DDK_CLOCK_GATE_INDEX_CSPI2 = 34,
DDK_CLOCK_GATE_INDEX_GACC = 35,
DDK_CLOCK_GATE_INDEX_EMI = 36,
DDK_CLOCK_GATE_INDEX_RTIC = 37,
DDK_CLOCK_GATE_INDEX_FIRI = 38,
DDK_CLOCK_GATE_INDEX_NFC = 44
} DDK_CLOCK_GATE_INDEX;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_GATE_MODE
//
// Clock gating modes supported by CCM clock gating registers.
//
//-----------------------------------------------------------------------------
typedef enum {
DDK_CLOCK_GATE_MODE_DISABLED = 0,
DDK_CLOCK_GATE_MODE_ENABLED_RUN = 1,
DDK_CLOCK_GATE_MODE_ENABLED_RUN_WAIT = 2,
DDK_CLOCK_GATE_MODE_ENABLED_ALL = 3
} DDK_CLOCK_GATE_MODE;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_BAUD_SOURCE
//
// Input source for baud clock generation.
//
//-----------------------------------------------------------------------------
typedef enum {
DDK_CLOCK_BAUD_SOURCE_MCUPLL = 0,
DDK_CLOCK_BAUD_SOURCE_USBPLL = 1,
DDK_CLOCK_BAUD_SOURCE_SERPLL = 2,
} DDK_CLOCK_BAUD_SOURCE;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_CKO_SRC
//
// Clock output source (CKO) signal selections.
//
//-----------------------------------------------------------------------------
typedef enum {
DDK_CLOCK_CKO_SRC_MCUPLL = 0,
DDK_CLOCK_CKO_SRC_IPG = 1,
DDK_CLOCK_CKO_SRC_USBPLL = 2,
DDK_CLOCK_CKO_SRC_PLLREF = 3,
DDK_CLOCK_CKO_SRC_FPM = 4,
DDK_CLOCK_CKO_SRC_AHB = 5,
DDK_CLOCK_CKO_SRC_ARM = 6,
DDK_CLOCK_CKO_SRC_SPLL = 7,
DDK_CLOCK_CKO_SRC_CKIH = 8,
DDK_CLOCK_CKO_SRC_EMI = 9,
DDK_CLOCK_CKO_SRC_HSP = 10,
DDK_CLOCK_CKO_SRC_NFC = 11,
DDK_CLOCK_CKO_SRC_PER = 12
} DDK_CLOCK_CKO_SRC;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_CKO_DIV
//
// Clock output source (CKO) divider selections.
//
//-----------------------------------------------------------------------------
typedef enum {
DDK_CLOCK_CKO_DIV_1 = 0,
DDK_CLOCK_CKO_DIV_2 = 1,
DDK_CLOCK_CKO_DIV_4 = 2,
DDK_CLOCK_CKO_DIV_8 = 3,
DDK_CLOCK_CKO_DIV_16 = 4,
} DDK_CLOCK_CKO_DIV;
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_DVFC_MODE
//
// Clock output source (CKO) divider selections.
//
//-----------------------------------------------------------------------------
typedef enum {
DDK_CLOCK_DVFC_MODE_NORMAL = (0x0 << CCM_PMCR1_DVGP_LSH),
DDK_CLOCK_DVFC_MODE_PANIC = (0x1 << CCM_PMCR1_DVGP_LSH),
DDK_CLOCK_DVFC_MODE_SUSPEND = (0x2 << CCM_PMCR1_DVGP_LSH),
DDK_CLOCK_DVFC_MODE_BUS_LOW = (0x4 << CCM_PMCR1_DVGP_LSH)
} DDK_CLOCK_DVFC_MODE;
//-----------------------------------------------------------------------------
//
// Type: DDK_IOMUX_PIN
//
// Specifies the functional pin name used to configure the IOMUX.
//
//-----------------------------------------------------------------------------
#ifdef VPMX31
typedef enum {
DDK_IOMUX_PIN_PAD2 = (0),
DDK_IOMUX_PIN_SD1CLK_B = (8),
DDK_IOMUX_PIN_CE_CONTROL = (16),
DDK_IOMUX_PIN_ATA_RESET_B = (24),
DDK_IOMUX_PIN_ATA_DMACK = (32),
DDK_IOMUX_PIN_ATA_DIOW = (40),
DDK_IOMUX_PIN_ATA_DIOR = (48),
DDK_IOMUX_PIN_ATA_CS1 = (56),
DDK_IOMUX_PIN_ATA_CS0 = (64),
DDK_IOMUX_PIN_SD1_DATA3 = (72),
DDK_IOMUX_PIN_SD1_DATA2 = (80),
DDK_IOMUX_PIN_SD1_DATA1 = (88),
DDK_IOMUX_PIN_SD1_DATA0 = (96),
DDK_IOMUX_PIN_SD1_CLK = (104),
DDK_IOMUX_PIN_SD1_CMD = (112),
DDK_IOMUX_PIN_D3_SPL = (120),
DDK_IOMUX_PIN_D3_CLS = (128),
DDK_IOMUX_PIN_D3_REV = (136),
DDK_IOMUX_PIN_CONTRAST = (144),
DDK_IOMUX_PIN_VSYNC3 = (152),
DDK_IOMUX_PIN_READ = (160),
DDK_IOMUX_PIN_WRITE = (168),
DDK_IOMUX_PIN_PAR_RS = (176),
DDK_IOMUX_PIN_SER_RS = (184),
DDK_IOMUX_PIN_LCS1 = (192),
DDK_IOMUX_PIN_LCS0 = (200),
DDK_IOMUX_PIN_SD_D_CLK = (208),
DDK_IOMUX_PIN_SD_D_IO = (216),
DDK_IOMUX_PIN_SD_D_O = (224),
DDK_IOMUX_PIN_DRDY0 = (232),
DDK_IOMUX_PIN_FPSHIFT = (240),
DDK_IOMUX_PIN_HSYNC = (248),
DDK_IOMUX_PIN_VSYNC0 = (256),
DDK_IOMUX_PIN_LD17 = (264),
DDK_IOMUX_PIN_LD16 = (272),
DDK_IOMUX_PIN_LD15 = (280),
DDK_IOMUX_PIN_LD14 = (288),
DDK_IOMUX_PIN_LD13 = (296),
DDK_IOMUX_PIN_LD12 = (304),
DDK_IOMUX_PIN_LD11 = (312),
DDK_IOMUX_PIN_LD10 = (320),
DDK_IOMUX_PIN_LD9 = (328),
DDK_IOMUX_PIN_LD8 = (336),
DDK_IOMUX_PIN_LD7 = (344),
DDK_IOMUX_PIN_LD6 = (352),
DDK_IOMUX_PIN_LD5 = (360),
DDK_IOMUX_PIN_LD4 = (368),
DDK_IOMUX_PIN_LD3 = (376),
DDK_IOMUX_PIN_LD2 = (384),
DDK_IOMUX_PIN_LD1 = (392),
DDK_IOMUX_PIN_LD0 = (400),
DDK_IOMUX_PIN_USBH2_DATA1 = (408),
DDK_IOMUX_PIN_USBH2_DATA0 = (416),
DDK_IOMUX_PIN_USBH2_NXT = (424),
DDK_IOMUX_PIN_USBH2_STP = (432),
DDK_IOMUX_PIN_USBH2_DIR = (440),
DDK_IOMUX_PIN_USBH2_CLK = (448),
DDK_IOMUX_PIN_USBOTG_DATA7 = (456),
DDK_IOMUX_PIN_USBOTG_DATA6 = (464),
DDK_IOMUX_PIN_USBOTG_DATA5 = (472),
DDK_IOMUX_PIN_USBOTG_DATA4 = (480),
DDK_IOMUX_PIN_USBOTG_DATA3 = (488),
DDK_IOMUX_PIN_USBOTG_DATA2 = (496),
DDK_IOMUX_PIN_USBOTG_DATA1 = (504),
DDK_IOMUX_PIN_USBOTG_DATA0 = (512),
DDK_IOMUX_PIN_USBOTG_NXT = (520),
DDK_IOMUX_PIN_USBOTG_STP = (528),
DDK_IOMUX_PIN_USBOTG_DIR = (536),
DDK_IOMUX_PIN_USBOTG_CLK = (544),
DDK_IOMUX_PIN_USB_BYP = (552),
DDK_IOMUX_PIN_USB_OC = (560),
DDK_IOMUX_PIN_USB_PWR = (568),
DDK_IOMUX_PIN_SJC_MOD = (576),
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