📄 startup.s
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str r0, [r2, #AIPSREG_PACR2_OFFSET]
str r0, [r2, #AIPSREG_PACR3_OFFSET]
str r0, [r2, #AIPSREG_OPACR0_OFFSET]
str r0, [r2, #AIPSREG_OPACR1_OFFSET]
str r0, [r2, #AIPSREG_OPACR2_OFFSET]
str r0, [r2, #AIPSREG_OPACR3_OFFSET]
str r0, [r2, #AIPSREG_OPACR4_OFFSET]
; AIPS regs (PACR0) are configured as follows:
; unbuffered writes (BW=0)
; enable supervisor protect (SP=1)
; disable write protect (WP=0)
; disable trusted protect (TP=0)
orr r0, r0, #(1 << (28+2))
str r0, [r1, #AIPSREG_PACR0_OFFSET]
str r0, [r2, #AIPSREG_PACR0_OFFSET]
; Set all MPRx to be non-bufferable, trusted for R/W,
; not forced to user-mode.
ldr r0, =(0x77777777)
str r0, [r1, #AIPSREG_MPR0_OFFSET]
str r0, [r1, #AIPSREG_MPR1_OFFSET]
str r0, [r2, #AIPSREG_MPR0_OFFSET]
str r0, [r2, #AIPSREG_MPR1_OFFSET]
;
; configure AHB crossbar switch (MAX) registers
;
;
; M0, M1 - L2 Cache, M0 is for linefills only, M1 is linefills and non-cached accesses
; M2 - Peripheral AHB
; M3 - RTIC
; M4 - SDMA
; M5 - USB
; S0 - GA/MBX
; S1 - EIM
; S2 - IPU
; S3 - AIPS1/ROM
; S4 - AIPS2/RAM
ldr r1, =CSP_BASE_REG_PA_MAX
; Master Priority (0 = highest priority)
; M4 > M2 > M3 > M5 > M0 > M1
; DMA > PAHB > RTIC > USB > L2M0 > L2M1
ldr r0, =(0x00302154)
; Master priority configured the same for all slaves
str r0, [r1, #MAX_MPR0_OFFSET]
str r0, [r1, #MAX_MPR1_OFFSET]
str r0, [r1, #MAX_MPR2_OFFSET]
str r0, [r1, #MAX_MPR3_OFFSET]
str r0, [r1, #MAX_MPR4_OFFSET]
; Slave control
; PARK - Ignored since PCTL not (0 << 0)
; PCTL - Park on last master (1 << 4)
; ARB - Fixed priority (0 << 8)
; HPE - High priority input disabled (0 << 16)
; HLP - Halt request has lowest priority (0 << 30)
; RO - Slave port registers can be written (0 << 31)
ldr r0, =(1 << 4)
; Slave control configured the same for all slaves
str r0, [r1, #MAX_SGPCR0_OFFSET]
str r0, [r1, #MAX_SGPCR1_OFFSET]
str r0, [r1, #MAX_SGPCR2_OFFSET]
str r0, [r1, #MAX_SGPCR3_OFFSET]
str r0, [r1, #MAX_SGPCR4_OFFSET]
; Master control
; AULB - Arbitration any time during undefined burst length (1 << 0)
ldr r0, =(1 << 0)
str r0, [r1, #MAX_MGPCR0_OFFSET]
str r0, [r1, #MAX_MGPCR1_OFFSET]
str r0, [r1, #MAX_MGPCR2_OFFSET]
str r0, [r1, #MAX_MGPCR3_OFFSET]
str r0, [r1, #MAX_MGPCR4_OFFSET]
str r0, [r1, #MAX_MGPCR5_OFFSET]
; Configure M3IF registers
ldr r1, =CSP_BASE_REG_PA_M3IF
; M3IF Control Register (M3IFCTL)
; MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
; MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
; MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
; MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
; MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
; MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
; MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
; MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
; ------------
; 0x00000040
;
ldr r0, =0x00000040
str r0, [r1, #M3IF_M3IFCTL_OFFSET]
; *** SPBA Bus Init ***
ldr r0, =CSP_BASE_REG_PA_SPBA
add r4, r0, #(SPBA_NUM_SHARED_PERIPH * 4)
; Peripheral rights (write value)
; RAR0 = ARM has access (1 << 0)
; RAR1 = DSP has access (1 << 1)
; RAR2 = DMA has access (1 << 2)
ldr r1, =7
; Peripheral rights (read value)
; RAR0 = ARM has access (1 << 0)
; RAR1 = DSP has access (1 << 1)
; RAR2 = DMA has access (1 << 2)
; ROI = ARM owns access (1 << 16)
; RMO = Requesting master has ownership (3 << 30)
ldr r2, =0xC0010007
spba_continue
str r1, [r0, #SPBA_PRR_OFFSET]
spba_check_loop
ldr r3, [r0, #SPBA_PRR_OFFSET]
cmp r2, r3
bne spba_check_loop
add r0, r0, #4
cmp r0, r4
ble spba_continue
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Determine the reason you are in the startup code, such as cold reset,
; watchdog reset, GPIO reset, and sleep reset.
;--------------------------------------------------------------------------
ldr r1, =CSP_BASE_REG_PA_CCM
; Read GPF bits in RCSR to determine if clocks and memory controller
; already initialized
ldr r0, [r1, #CCM_RCSR_OFFSET]
mov r2, r0
ands r0, r0, #(1 << 4)
bne load_pbc_config
; Set flag for next Startup entry to skip initialization
orr r2, r2, #(1 << 4)
str r2, [r1, #CCM_RCSR_OFFSET]
;load default config
mov r6, #1
ldr r7, =PBC_BSTAT2_DEFAULT
b load_pbc_done
load_pbc_config
mov r6, #0
ldr r0, =PBC_RAM_START
ldrh r7, [r0, #PBC_BSTAT2_OFFSET]
; same config as last time?
ldr r1, =PBC_BSTAT2_DEFAULT
cmp r7, r1
beq cache_init
load_pbc_done
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Configure the GPIO lines per the requirements of the board. GPIO lines
; must be enabled for on-board features like LED.
;--------------------------------------------------------------------------
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Configure the memory controller, set refresh frequency, and enable
; clocks. Program data width and memory timing values and power up the
; banks.
;--------------------------------------------------------------------------
; Configure CS4 so we can read PBC user switches
ldr r1, =CSP_BASE_REG_PA_WEIM
ldr r0, =0x0000D843
;ldr r0, =0x0000DCF6
str r0, [r1, #WEIM_CSCR4U_OFFSET]
ldr r0, =0x22252521
;ldr r0, =0x444A4541
str r0, [r1, #WEIM_CSCR4L_OFFSET]
ldr r0, =0x22220A00
;ldr r0, =0x44443302
str r0, [r1, #WEIM_CSCR4A_OFFSET]
; zhongtao@
; Configure CS5 to operate Ethernet(CS8900a) chip
ldr r1, =CSP_BASE_REG_PA_WEIM
ldr r0, =0x0000D843
;ldr r0, =0x0000DCF6
str r0, [r1, #WEIM_CSCR5U_OFFSET]
ldr r0, =0x22252521
;ldr r0, =0x444A4541
str r0, [r1, #WEIM_CSCR5L_OFFSET]
ldr r0, =0x22220A00
;ldr r0, =0x44443302
str r0, [r1, #WEIM_CSCR5A_OFFSET]
; zhongtao#
; Enable IPU DI to get acknowledge for max_podf value change
ldr r1, =CSP_BASE_REG_PA_IPU
; IPU configuration register (IPU_CONF):
; DI_EN = Display interface enabled = (1 << 6) = 0x00000040
; ------------
; 0x00000040
ldr r0, =0x00000040
str r0, [r1]
ldr r1, =CSP_BASE_REG_PA_CCM
; Control register (CCMR):
;
; FPME = FPM enabled = (1 << 0) = 0x00000001
; PRCS = CKIL is PLL ref = (1 << 1) = 0x00000002
; MPE = MCU PLL enabled = (1 << 3) = 0x00000008
; SBYCS = Enabled in standby = (1 << 4) = 0x00000010
; ROMW = All masters 1 WS = (3 << 5) = 0x00000060
; MDS = MCU PLL is source = (0 << 7) = 0x00000000
; SPE = serial PLL enabled = (1 << 8) = 0x00000100
; UPE = USB PLL enabled = (1 << 9) = 0x00000200
; WAMO = masked all but DSM = (0 << 10) = 0x00000000
; FIRS = FIRI source usb_clk = (1 << 11) = 0x00000800
; LPM = wait mode = (0 << 14) = 0x00000000
; RAMW = All masters 1 WS = (3 << 16) = 0x00030000
; SSI1S = SSI1 source serial_clk = (2 << 18) = 0x00080000
; SSI1S = SSI2 source serial_clk = (2 << 21) = 0x00400000
; PERCS = per_clk source ipg_clk = (1 << 24) = 0x01000000
; CSCS = CSI source SRPLL = (1 << 25) = 0x02000000
; FPMF = FPM factor 1024 = (1 << 26) = 0x04000000
; WBEN = well bias disabled = (0 << 27) = 0x00000000
; VSTBY = no standby = (0 << 28) = 0x00000000
; L2PG = no L2 power gating (0 << 29) = 0x00000000
; ------------
; 0x074B0B7B
ldr r0, =0x074B0B7B
str r0, [r1, #CCM_CCMR_OFFSET]
; Read PBC user switches to determine clock configuration
ldr r5, =CSP_BASE_MEM_PA_CS4
ldrh r5, [r5, #PBC_BSTAT2_OFFSET]
;zhongtao@
mov r5, r7
;zhongtao#
; Check for forced alternate clocking
ands r0, r5, #BSP_PBC_DSW_ALT_CLK
bne CLK_ALT
; Configure the Serial PLL
;
; SERPLL = (CKIL) * FPM * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (32768) * 1024 * 2 * (3 + 14/(49+1)) / (1+1)
; = 220.117073 MHz
;
; MFN = 14 = (14 << 0) = 0x0000000E
; MFI = 3 = (3 << 10) = 0x00000C00
; MFD = 49 = (49 << 16) = 0x00310000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x00310C0E
ldr r0, =0x00310C0E
str r0, [r1, #CCM_SPCTL_OFFSET]
; Configure the USB PLL
;
; USBPLL = (CKIL) * FPM * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (32768) * 1024 * 2 * (3 + 56/(96+1)) / (0+1)
; = 240.069853 MHz
;
; MFN = 56 = (56 << 0) = 0x00000038
; MFI = 3 = (3 << 10) = 0x00000C00
; MFD = 96 = (96 << 16) = 0x00600000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x00600C38
ldr r0, =0x00600C38
str r0, [r1, #CCM_UPCTL_OFFSET]
; Determine AHB clock configuration
and r0, r5, #BSP_PBC_DSW_AHB_CLK
cmp r0, #BSP_PBC_DSW_AHB_66
beq CLK_AHB_66
; Fall though to CLK_AHB_133
CLK_AHB_133
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 532 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 266 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 133 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 4 = 133 MHz
; IPG_CLK = HCLK / 2 = 66.5 MHz
; NFC_CLK = HCLK / 6 = 22.167 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /1 = (1 << 0) = 0x00000001
; MAX_PODF = /4 = (3 << 3) = 0x00000018
; IPG_PODF = /2 = (1 << 6) = 0x00000040
; NFC_PODF = /6 = (5 << 8) = 0x00000500
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831D59
ldr r0, =0xFF831D59
str r0, [r1, #CCM_PDR0_OFFSET]
b CLK_MCUPLL_532
CLK_AHB_66
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 532 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 266 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 133 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 8 = 66.5 MHz
; IPG_CLK = HCLK / 1 = 66.5 MHz
; NFC_CLK = HCLK / 3 = 22.167 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /2 = (1 << 0) = 0x00000001
; MAX_PODF = /8 = (7 << 3) = 0x00000038
; IPG_PODF = /1 = (0 << 6) = 0x00000000
; NFC_PODF = /3 = (2 << 8) = 0x00000200
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831A39
ldr r0, =0xFF831A39
str r0, [r1, #CCM_PDR0_OFFSET]
CLK_MCUPLL_532
; MCU PLL control (MPCTL)
;
; MCU_CLK = (CKIL)*FPM * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (32768)*1024 * 2 * (7 + 51/(54+1)) / (0+1)
; = 531990267 MHz
;
; MFN = 51 = (51 << 0) = 0x00000033
; MFI = 7 = (7 << 10) = 0x00001C00
; MFD = 54 = (54 << 16) = 0x00360000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x00361C33
ldr r0, =0x00361C33
str r0, [r1, #CCM_MPCTL_OFFSET]
b WEIM_CONFIG
CLK_ALT
b CLK_ALT
WEIM_CONFIG
;
; Configure wireless external interface module (WEIM)
;
;
; Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
;
ldr r1, =CSP_BASE_MEM_PA_CS0
ldr r0, =0xF0F0
strh r0, [r1]
; 1st command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xAAAA
strh r0, [r2]
; 2nd command
ldr r2, =0x554
add r2, r2, r1
ldr r0, =0x5555
strh r0, [r2]
; 3rd command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xD0D0
strh r0, [r2]
; Write flash config register
ldr r0, =0x56CA
strh r0, [r2]
; Flash reset command
ldr r0, =0xF0F0
strh r0, [r1]
ldr r1, =CSP_BASE_REG_PA_WEIM
; CS0 control (upper)
; EDC - 3 extra dead cycles (3 << 0) = 0x00000003
; WWS - 0 extra write wait states (0 << 4) = 0x00000000
; EW - Posedge DTACK (0 << 7) = 0x00000000
; WSC - 12 wait states (12 << 8) = 0x00000C00
; CNC - 3 CS negation cycles (3 << 14) = 0x0000C000
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