display.c

freescale i.mx31 BSP CE5.0全部源码

    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_DRDY0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_REV, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_CONTRAST, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_SPL, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_CLS, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);

    // Turn on LCD via PBC
    OUTREG16(&g_pPBC->BCTRL1_SET, CSP_BITFMASK(PBC_BCTRL1_SET_LCDON));
    
    // Enable DI and SDC
    SETREG32(&g_pIPU->IPU_CONF,
                CSP_BITFVAL( IPU_IPU_CONF_DI_EN, IPU_IPU_CONF_DI_EN_ENABLE)|
                CSP_BITFVAL( IPU_IPU_CONF_SDC_EN, IPU_IPU_CONF_SDC_EN_ENABLE));

    // Enable DMA SDC Channel 1
    INSREG32BF(&g_pIPU->IDMAC_CHA_EN,
                IPU_DMA_CHA_DMASDC_0, IPU_ENABLE);
	
    // Enable SDC background
    // Set BG_EN = 1 (Background is enabled)
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_BG_EN, IPU_ENABLE);
	
    // Set DMA SDC Channel 0 as ready
    INSREG32BF(&g_pIPU->IPU_CHA_BUF0_RDY,
               IPU_DMA_CHA_DMASDC_0, IPU_DMA_CHA_READY);
               

}

// Initialize the clock to IPU and SDC registers
void SDC_Initialize(void)
{
	// map registers
    g_pIOMUX = (PCSP_IOMUX_REGS) OALPAtoUA(CSP_BASE_REG_PA_IOMUXC);
    g_pIPU = (PCSP_IPU_REGS) OALPAtoUA(CSP_BASE_REG_PA_IPU);
    g_pCCM = (PCSP_CCM_REGS) OALPAtoUA(CSP_BASE_REG_PA_CCM);
    g_pPBC = (PCSP_PBC_REGS) OALPAtoUA(BSP_BASE_REG_PA_PBC_BASE);
    
	// Enable clock to IPU -- bits 22-23 of CGR1
	// Read in current value, "or" it with bits 22-23, write the value back to the register
	OUTREG32( &g_pCCM->CGR[1], ((INREG32(&g_pCCM->CGR[1]) | 0xC00000)) );	

	    //----- General configuration

    // Set little endian
    INSREG32BF(&g_pIPU->IPU_CONF,
                IPU_IPU_CONF_PXL_ENDIAN, IPU_LITTLE_ENDIAN);


    //----- Display interface configuration


    //... SDC_COM_CONF
    OUTREG32( &g_pIPU->SDC_COM_CONF,
             //.. SDC mode
              CSP_BITFVAL(IPU_SDC_COM_CONF_SDC_MODE, IPU_SDC_MODE_TFT_COLOR)|
             //.. sharp pannel enable
              CSP_BITFVAL(IPU_SDC_COM_CONF_SHARP, 0x1)|
             //.. dual mode enable
              CSP_BITFVAL(IPU_SDC_COM_CONF_DUAL_MODE, 0));

    //... SDC_HOR_CONF
    OUTREG32( &g_pIPU->SDC_HOR_CONF,
              //.. display width for tearing and Vsync calculation
              CSP_BITFVAL(IPU_SDC_HOR_CONF_SCREEN_WIDTH, 0x112)|
              //.. horizontal synchronization pulse
              CSP_BITFVAL(IPU_SDC_HOR_CONF_H_SYNC_WIDTH, 0));

    //... SDC_VER_CONF
    OUTREG32( &g_pIPU->SDC_VER_CONF,
              //..line/pixel resolution
              CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH_L, 0x1)|
              //..display height for tearing and Vsync calculation
              CSP_BITFVAL(IPU_SDC_VER_CONF_SCREEN_HEIGHT, 0x173)|
              //..vsync size
              CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH, 0x1));

    //... SDC_SHARP_CONF_1
    OUTREG32( &g_pIPU->SDC_SHARP_CONF_1,
              //..cls rise delay
              CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_CLS_RISE_DELAY, 0x2)|
              //..ps fall delay
              CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_PS_FALL_DELAY, 0x1)|
              //..rev toggle delay
              CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_REV_TOGGLE_DELAY, 0xfd));

    //... SDC_SHARP_CONF_2
    OUTREG32(&g_pIPU->SDC_SHARP_CONF_2,
              //..cls fall delay
              CSP_BITFVAL( IPU_SDC_SHARP_CONF_2_CLS_FALL_DELAY, 0xf4)|
              //..ps rise delay
              CSP_BITFVAL( IPU_SDC_SHARP_CONF_2_PS_RISE_DELAY, 0xf5));

    //... DI_DISP_IF_CONF
    OUTREG32(&g_pIPU->DI_DISP_IF_CONF,
              //..data mask
              CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_DATAMASK, 0)|
              // select interface display clock
              CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_SEL, 0)|
              // display clock idle enable
              CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_IDLE, 0x1));

    //... DI_DISP_SIG_POL
    OUTREG32(&g_pIPU->DI_DISP_SIG_POL,
              //..1: inverse data polarity
              CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DATA_POL, 0x1)|
              //..display interface clock polarity
              CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_CLK_POL, 0x1)|
              //..1: active high horizontal signal polarity
              CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_HSYNC_POL, 0x1)|
              //..1: active high vertical signal polarity
              CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_VSYNC_POL, 0)|
              // output enable polarity
              CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DRDY_SHARP_POL, 0));


    // HSP_CLK = 133 MHz
    //
    // DI_CLK = HSP_CLK * HSP_CLOCK_PER = 133 MHz
    //        ==> HSP_CLOCK_PER = 1
    // these are 7 bit fields iiiffff
    // where i = integer part and f = fractional part of the value
    OUTREG32(&g_pIPU->DI_HSP_CLK_PER,
              CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_1, 1 << 4) |
              CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_2, 1 << 4));

    // DI_CLK = 66.5 MHz
    //
    // 4.5MHz < DISP3_IF_CLK < 6.8MHz (per Sharp spec)
    //
    // DI_DISP3_TIME_CONF = DI_CLK / DISP3_IF_CLK_PER_WR = 133 MHz / 20 = 6.65MHz
    // DI_DISP3_TIME_CONF = DI_CLK / DISP3_IF_CLK_PER_WR = 133 MHz / 28 = 4.75MHz
    //
    OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
              //.. period
              CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, 28 << 4)|
              //..write strobe start
              CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR, 0)|
              //..write strobe end
              CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, 14 << 2));

    //... DI_DISP_ACC_CC
    INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                // display clock cycles number (data access)
                IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D, 0);


    //... DI_DISP3_B0_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B0_MAP,
                // set0; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS0, 0x5)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS2, 0)|

                // set0; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M7, 0));



    //... DI_DISP3_B1_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B1_MAP,
                // set1; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS0, 0xb)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS2, 0)|

                // set1; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M7, 0));


    //... DI_DISP3_B2_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B2_MAP,
                // set2; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS0, 0x11)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS2, 0)|

                // set2; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M7, 0));


    //----- SDC Configuration
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_GWSEL, IPU_SDC_COM_CONF_GWSEL_BG);
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_SDC_GLB_LOC_A, 1);

#ifdef VPMX31
    OUTREG32(&g_pIPU->SDC_BG_POS,
                CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, 0x0)|
                CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, 0x0));

    OUTREG32(&g_pIPU->SDC_FG_POS,
                CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, 0x0)|
                CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, 0x0));
#else
    OUTREG32(&g_pIPU->SDC_BG_POS,
                CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, 0x3)|
                CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, 0x8));

    OUTREG32(&g_pIPU->SDC_FG_POS,
                CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, 0x3)|
                CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, 0x8));
#endif


    //----- IDMAC Configuration

    // Set no double-buffer, use buf0
    INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
    INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);


    // Set buffer 0 as current buffer (non double buffered)
    INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
    INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);

    // Set high priority for DMA SDC Channel 0
    INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
                IPU_DMA_CHA_DMASDC_0, 1);

    // Set high priority for DMA SDC Channel 1
    INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
                IPU_DMA_CHA_DMASDC_1, 1);


    // Select source of SDC channel as ARM
    OUTREG32(&g_pIPU->IPU_FS_DISP_FLOW,
                CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL, FLOW_ARM)|
                CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL, FLOW_ARM));

    // Turn contrast fully on
    OUTREG32(&g_pIPU->SDC_CUR_BLINK_PWM_CTRL,
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_SCR, 1)|
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN, 1)|
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_PWM, 0x8F));

    _init_dma(240, 320, 16, FALSE, SDC_DMA_CHANNEL);
    
    

}

void DisplayDriverInitialize (PDISPLAYCONFIGURATION pConfiguration)
{
    EdbgOutputDebugString ("DisplayDriverInitialize. pFrameBuffer = 0x%x\n\r", IMAGE_BOOT_DISPLAY_RAM_START);

    // Initialize the display configuration
    //
    pConfiguration->dwFrameBufferBasePhysical = IMAGE_BOOT_DISPLAY_RAM_START;
    pConfiguration->pFrameBuffer = (PBYTE) OALPAtoVA(pConfiguration->dwFrameBufferBasePhysical,FALSE);
    pConfiguration->cxScreen = 240;
    pConfiguration->cyScreen = 320;
    pConfiguration->usBitsPerPixel = 16;
    pConfiguration->fRotated = FALSE;
    pConfiguration->usXScale = 1;
    pConfiguration->usYScale = 1;   
    
    // Configure MX31 Synchronous Display Controller
    SDC_Initialize();
    SDC_Configure();
}