display.c

freescale i.mx31 BSP CE5.0全部源码

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995, 1996, 1997, 1998  Microsoft Corporation
--*/

#include <bsp.h>
#include "pmc_loader.h"
#include <pmcdisplay.h>

// Defines
#define FLOW_ARM                    0
#define SDC_DMA_CHANNEL             IPU_DMA_CHA_DMASDC_0_LSH    //  background

// i.MX31 Registers
PCSP_CCM_REGS g_pCCM = NULL;
PCSP_IOMUX_REGS g_pIOMUX = NULL;
PCSP_IPU_REGS g_pIPU;
PCSP_PBC_REGS g_pPBC;

// Init the IPU DMA module
static void _init_dma(int width, int height, int bpp, BOOL vFlip, const channel)
{
    UINT32 bpp_code, npb_code, sat_code, bam_code, ofs[4], wid[4];
    UINT32 ima_addr = 0;

    //=================================
    // Configure First 132 bit word
    //=================================

    // Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
    OUTREG32(&g_pIPU->IPU_IMA_ADDR,
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel ))|
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 0));

    //...0th 32 bit word
    // XV [9:0], YV [19:10], XB [31:20]
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_XV, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_YV, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_XB, 0));

    //...1st 32 bit word
    // YB [11:0], SCE [12], RESERVED [13], NSB [14], LNPB [20:15], SX [30:21],
    // SY~ [31]
    // - Set NSB
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_YB, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCE, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NSB, 1)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LNPB, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SX, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_SY, 0));

    //...2nd 32 bit word
    // ~SY [8:0], NS [18:9], SM [28:10] SDX~ [31:29]
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_HIGH_SY, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NS, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SM, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_SDX, 0));

    //...3rd 32 bit word
    // ~SDX [1:0], SDY [6:2], SDRX [7], SDRY [8], SCRQ [9], RESERVED [11:10]
    // - FW [23:12], FH~ [31:24]
    // - Set FW & FH
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_HIGH_SDX, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDY, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDRX, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDRY, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCRQ, 0)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_FW, (width - 1))|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_FH, (height - 1)));

    //...4th 32 bit word
    // ~FH [3:0]
    // NOTE: this takes care of the upper four bits in the FH field
    OUTREG32(&g_pIPU->IPU_IMA_DATA, ((height - 1) >> 8));


    //=================================
    // Configure Second 132 bit word
    //=================================

    if ( channel == SDC_DMA_CHANNEL )
    {
        // Set IPU IPU_IMA_ADDR (IPU Internal Memory Access Address)
        // MEM_NU = 0x0001 (CPM)
        // ROW_NU = 2*N + 1 (N is channel number)
        // WORD_NU = 0
        OUTREG32(&g_pIPU->IPU_IMA_ADDR,
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU,(2 * channel + 1))|
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 0));

        //...parameters for YUV/RGB interleaved - 2nd 132 bit word

        //...0th 32 bit word
        // EBA0 [31:0]
        // Set buffer #1 to physical frame buffer address
        OUTREG32(&g_pIPU->IPU_IMA_DATA, IMAGE_BOOT_DISPLAY_RAM_START);

        //...1st 32 bit word
        // EBA1 [31:0]
        OUTREG32(&g_pIPU->IPU_IMA_DATA, 0);
    }
    else
    {
        //..skip over EBA0 and EBA1 for the viewfinder mode

        //.. Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
        OUTREG32(&g_pIPU->IPU_IMA_ADDR,
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel + 1))|
                CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 2));
    }

    //...2nd 32 bit word

    // Default access type to 32-bit
    sat_code = 2;

    switch (bpp)
    {
        case 32:
            bpp_code = 0;
            npb_code = 8-1;
            ofs[0] = 0;
            ofs[1] = 8;
            ofs[2] = 16;
            ofs[3] = 24;
            wid[0] = 8-1;
            wid[1] = 8-1;
            wid[2] = 8-1;
            wid[3] = 8-1;
            break;

        case 24:
            bpp_code = 1;
            npb_code = 10-1;
            sat_code = 0;
            ofs[0] = 0;
            ofs[1] = 8;
            ofs[2] = 16;
            ofs[3] = 0;
            wid[0] = 8-1;
            wid[1] = 8-1;
            wid[2] = 8-1;
            wid[3] = 0;
            break;

        case 16:
            bpp_code = 2;
            npb_code = 16-1;
            ofs[0] = 0;
            ofs[1] = 5;
            ofs[2] = 11;
            ofs[3] = 0;
            wid[0] = 5-1;
            wid[1] = 6-1;
            wid[2] = 5-1;
            wid[3] = 0;
            break;

        case 8:
            bpp_code = 3;
            npb_code = 32-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 8-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        case 4:
            bpp_code = 4;
            npb_code = 32-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 4-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        case 1:
            bpp_code = 5;
            npb_code = 64-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 1-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        default:
            bpp_code = 7;
        // TODO:  Should report error here.  bpp_code is reserved.
        break;
    }

    bam_code = vFlip ? 1 : 0;

    // - BPP [2:0], SL [16:3], PFS [19:17], BAM [24:20], NPB [30:25],
    // - RESERVED [31]
    // - Set BPP to 24bpp (1)
    // - Set SL (Scaling Factor) to bytes_pp * width
    // - Set PFS (Packing) to RGB (%100)
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BPP, bpp_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SL, ((width * bpp / 8) - 1))|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_PFS, 0x4)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BAM, bam_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NPB, npb_code));

    //...3rd 32 bit word
    // SAT [1:0], SCC [2], OFS0 [7:3], 0FS1 [12:8], OFS2 [17:13], OFS3 [22:18]
    // - WID0 [25:23], WID1 [28:26], WID2 [31:29]
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SAT, sat_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCC, 0)|

                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS0, ofs[0]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS1, ofs[1]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS2, ofs[2]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS3, ofs[3]) |

                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID0, wid[0]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID1, wid[1]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID2, wid[2]));

    //...4th 32 bit word
    // WID3 [2:0], DEC_SEL [3],
    // Set WID3 (7 - 8 bit size), Color component 3 width (Alpha)
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL(IPU_IPU_IMA_DATA_PARAM_WID3, wid[3]));
}

// Configure the IOMux lines and enable the SDC
void SDC_Configure(void) 
{

	// Configure IOMUX to request IPU SDC pins
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD1, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD2, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD3, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD4, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD5, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD6, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD7, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD8, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD9, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD10, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD11, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD12, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD13, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD14, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD15, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD16, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD17, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_VSYNC3, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_HSYNC, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_FPSHIFT, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);