main.c

freescale i.mx31 BSP CE5.0全部源码

        // Clear all autoboot flags
        pBootCfg->ConfigFlags &= ~CONFIG_FLAGS_AUTOBOOT;
    }
    else
    {
        // set autoboot flag
        pBootCfg->ConfigFlags &= ~CONFIG_FLAGS_AUTOBOOT;

        bExitMenu = FALSE;
        do {
            EdbgOutputDebugString("\r\nAutoboot Selection Menu\r\n");
            EdbgOutputDebugString("1) Autoboot from NOR\r\n");
            EdbgOutputDebugString("2) Autoboot from NAND\r\n");
            EdbgOutputDebugString("Enter your selection: ");
            while(1)
            {
                selection = OEMReadDebugByte();
                if((selection >= '1' && selection <= '2'))
                    break;
            }

            EdbgOutputDebugString ("%c\r\n\r\n", selection);

            switch(selection)
            {
                case '1':
                    pBootCfg->ConfigFlags |= CONFIG_FLAGS_AUTOBOOT;
                    pBootCfg->BootDevice = CONFIG_AUTOBOOT_DEVICE_NOR;
                    // Return To Main Menu.
                    bExitMenu = TRUE;
                    break;
                case '2':
                    pBootCfg->ConfigFlags |= CONFIG_FLAGS_AUTOBOOT;
                    pBootCfg->BootDevice = CONFIG_AUTOBOOT_DEVICE_NAND;
                    // Return To Main Menu.
                    bExitMenu = TRUE;
                    break;
                default:
                    break;
            }
        } while(bExitMenu == FALSE);
    }
}

void SpinForever(void)
{
    CSP_PBC_REGS *pPBC;

    // On both on board leds
    pPBC = (PCSP_PBC_REGS)OALPAtoVA((UINT32)BSP_BASE_REG_PA_PBC_BASE, FALSE);
    OUTREG16(&pPBC->BCTRL1_SET, CSP_BITFMASK(PBC_BCTRL1_SET_LED0));
    OUTREG16(&pPBC->BCTRL1_SET, CSP_BITFMASK(PBC_BCTRL1_SET_LED1));

    OALMSG(OAL_ERROR, (TEXT("Halting system\r\n")));
    while(1);
}

void UpdatePBCRam(BOOT_CFG *pBootCfg)
{

    //#define BSP_PBC_DSW_KITL            (1 << 0)    // SW3_8:  ON = ACTIVE, OFF = PASSIVE 
    //#define BSP_PBC_DSW_L2                (1 << 1)    // SW3_7:  ON = L2 enabled, OFF = L2 disabled
    //#define BSP_PBC_DSW_AHB_CLK     (1 << 2)    // SW3_6:  ON = 133MHz, OFF = 66MHz
    //#define BSP_PBC_DSW_ARM_CLK     (1 << 3)    // SW3_5:  ON = 532MHz, OFF = 266MHz
    //#define BSP_PBC_DSW_ALT_CLK     (1 << 4)    // SW3_4:  ON = 26M, OFF = Force alternate clocking
    #define BSP_PBC_DSW_DPTC           (1 << 5)    // SW3_3:  ON = ACTIVE, OFF = PASSIVE 
    #define BSP_PBC_DSW_DVFS           (1 << 6)    // SW3_2:  ON = ACTIVE, OFF = PASSIVE 

    CSP_PBC_REGS *pPBC;
    UINT16 BSTAT2;

    pPBC = (PCSP_PBC_REGS)OALPAtoVA((UINT32)BSP_BASE_REG_PA_PBC_BASE, FALSE);

    BSTAT2 = INREG16(&pPBC->BSTAT2);

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_KITL_PASSIVE) == 0){
        BSTAT2 &= ~( BSP_PBC_DSW_KITL);
    } else {
        BSTAT2 |= BSP_PBC_DSW_KITL;
    }

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_L2CACHE) == 0){
        BSTAT2 |= BSP_PBC_DSW_L2;
    } else {
        BSTAT2 &= ~(BSP_PBC_DSW_L2);
    }

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_AHBCLK) == 0){
        BSTAT2 |= BSP_PBC_DSW_AHB_CLK;
    } else {
        BSTAT2 &= ~(BSP_PBC_DSW_AHB_CLK);
    }

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_ARMCLK) == 0){
        BSTAT2 |= BSP_PBC_DSW_ARM_CLK;
    } else {
        BSTAT2 &= ~(BSP_PBC_DSW_ARM_CLK);
    }

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_DPTC) == 0){
        BSTAT2 |= BSP_PBC_DSW_DPTC;
    } else {
        BSTAT2 &= ~(BSP_PBC_DSW_DPTC);
    }

    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_DVFS) == 0){
        BSTAT2 |= BSP_PBC_DSW_DVFS;
    } else {
        BSTAT2 &= ~(BSP_PBC_DSW_DVFS);
    }

    OUTREG16(&pPBC->BSTAT2, BSTAT2);


    //update SW2A voltage
    if((pBootCfg->ConfigFlags & CONFIG_FLAGS_SW2A) == 0){
        // SW1A 1.7V
        OALWritePmicRegister(0x1a, 0x3F, 0x23);
        OALWritePmicRegister(0x1a, 0x3F, 0x23);

    } else {
        // SW1A 1.8V
        OALWritePmicRegister(0x1a, 0x3F, 0x24);
        OALWritePmicRegister(0x1a, 0x3F, 0x24);

    }
    
}


void OALInitPmic(void)
{
    PCSP_IOMUX_REGS pIOMUX;
    PCSP_CSPI_REG pCSPI2;
    PCSP_CCM_REGS pCCM;

    pIOMUX = (PCSP_IOMUX_REGS) OALPAtoUA(CSP_BASE_REG_PA_IOMUXC);
    if (pIOMUX == NULL)
    {
        return;
    }

    pCSPI2 = (PCSP_CSPI_REG) OALPAtoUA(CSP_BASE_REG_PA_CSPI2);
    if (pCSPI2 == NULL)
    {
        return;
    }

    pCCM = (PCSP_CCM_REGS) OALPAtoUA(CSP_BASE_REG_PA_CCM);
    if (pCCM == NULL)
    {
        return;
    }

    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_SPI_RDY, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_SCLK, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_SS2, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_SS1, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_SS0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_MISO, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSPI2_MOSI, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);


    // enable CSPI2 clock
    OUTREG32(&pCCM->CGR[2], (INREG32(&pCCM->CGR[2]) | 0x00000030));

    // CSPI2 configurate
    OUTREG32(&pCSPI2->CONREG, 0x2031f83);
    OUTREG32(&pCSPI2->INTREG, 0);
    OUTREG32(&pCSPI2->DMAREG, 0);
    OUTREG32(&pCSPI2->TESTREG, 0);

}


int OALReadPmicRegister(unsigned int addr)
{
    unsigned int rc;
    unsigned int packet = 0;
    unsigned int delay = 0xFFFF;

    PCSP_CSPI_REG pCSPI2;

    pCSPI2 = (PCSP_CSPI_REG) OALPAtoUA(CSP_BASE_REG_PA_CSPI2);
    if (pCSPI2 == NULL)
    {
        return -1;
    }

    packet |= (addr & 0x3F) << 25;
    packet |= (0 << 31);
    
    OUTREG32(&pCSPI2->TXDATA, packet);
    INSREG32BF(&pCSPI2->CONREG, CSPI_CONREG_XCH, CSPI_CONREG_XCH_EN);    

    do{
	    delay--;
    }while((INREG32(&pCSPI2->CONREG) & CSP_BITFMASK(CSPI_CONREG_XCH)) && delay);

    if(!delay){
       return -1;
    }

    rc = INREG32(&pCSPI2->RXDATA);

    return rc;
}

int OALWritePmicRegister(unsigned int addr, unsigned int mask, unsigned int data)
{
    unsigned int content;
    unsigned int packet = 0;
    unsigned int delay = 0xFFFF;

    PCSP_CSPI_REG pCSPI2;

    pCSPI2 = (PCSP_CSPI_REG) OALPAtoUA(CSP_BASE_REG_PA_CSPI2);
    if (pCSPI2 == NULL)
    {
        return -1;
    }


    content = OALReadPmicRegister(addr);

    content &= ~mask;
    content |= data & mask;


    packet |= content & 0xFFFFFF;
    packet |= (addr & 0x3F) << 25;
    packet |= (1 << 31);


    OUTREG32(&pCSPI2->TXDATA, packet);
    INSREG32BF(&pCSPI2->CONREG, CSPI_CONREG_XCH, CSPI_CONREG_XCH_EN);    

    do{
	    delay--;
    }while((INREG32(&pCSPI2->CONREG) & CSP_BITFMASK(CSPI_CONREG_XCH)) && delay);

    if(!delay){
       return -1;
    }

    return 0;    
}


void OALInitDevice(void)
{
    PCSP_IOMUX_REGS pIOMUX;
    PCSP_GPIO_REGS pGPIO2;
    PCSP_GPIO_REGS pGPIO3;

    pIOMUX = (PCSP_IOMUX_REGS) OALPAtoUA(CSP_BASE_REG_PA_IOMUXC);
    if (pIOMUX == NULL)
    {
        return;
    }

    pGPIO2 = (PCSP_GPIO_REGS) OALPAtoUA(CSP_BASE_REG_PA_GPIO2);
    if (pGPIO2 == NULL)
    {
        return;
    }

    pGPIO3 = (PCSP_GPIO_REGS) OALPAtoUA(CSP_BASE_REG_PA_GPIO3);
    if (pGPIO3 == NULL)
    {
        return;
    }


    // LCD  
    // -----------------------------------------------------
    // Turn off        DDK_IOMUX_PIN_SD_D_I    MCU3_20     active low
    // Power on      DDK_IOMUX_PIN_SER_RS    MCU3_25     active low

    // turn on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_SD_D_I, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 20)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) | (1 << 20)));

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_SER_RS, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 25)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) & ~(1 << 25)));

    // TVIN
    // -----------------------------------------------------
    // Power down    DDK_IOMUX_PIN_SIMPD0    MCU2_3    active low

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_SIMPD0, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO2->GDIR, (INREG32(&pGPIO2->GDIR) | (1 << 3)));
    OUTREG32(&pGPIO2->DR, (INREG32(&pGPIO2->DR) | (1 << 3)));


    // TVOUT
    // -----------------------------------------------------
    // Power down    


    // HDD
    // -----------------------------------------------------
    // Power on    DDK_IOMUX_PIN_GPIO3_0    MCU3_0    active high

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_GPIO3_0, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 0)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) | (1 << 0)));

    // FM
    // -----------------------------------------------------
    // Power on    DDK_IOMUX_PIN_SD_D_CLK    MCU3_22    active low

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_SD_D_CLK, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 22)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) & ~(1 << 22)));

    // GPS
    // -----------------------------------------------------
    // Power on    DDK_IOMUX_PIN_CSI_D5    MCU3_5    active low

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSI_D5, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 5)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) & ~(1 << 5)));

    // IRDA
    // -----------------------------------------------------
    // Power on    DDK_IOMUX_PIN_CSI_D4    MCU3_4    active low

    // power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_CSI_D4, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO3->GDIR, (INREG32(&pGPIO3->GDIR) | (1 << 4)));
    OUTREG32(&pGPIO3->DR, (INREG32(&pGPIO3->DR) & ~(1 << 4)));


    // IO3V3
    // -----------------------------------------------------
    // Power on    DDK_IOMUX_PIN_SVEN0    MCU2_0    active high

    //Power on
    OAL_IOMUX_SET_MUX(pIOMUX, DDK_IOMUX_PIN_SVEN0, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_GPIO);
    OUTREG32(&pGPIO2->GDIR, (INREG32(&pGPIO2->GDIR) | (1 << 0)));
    OUTREG32(&pGPIO2->DR, (INREG32(&pGPIO2->DR) | (1 << 0)));


    // Init PMIC
    OALInitPmic();
   
}

//------------------------------------------------------------------------------
// END OF FILE
//------------------------------------------------------------------------------