📄 startup.s
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ldr r1, =7
; Peripheral rights (read value)
; RAR0 = ARM has access (1 << 0)
; RAR1 = DSP has access (1 << 1)
; RAR2 = DMA has access (1 << 2)
; ROI = ARM owns access (1 << 16)
; RMO = Requesting master has ownership (3 << 30)
ldr r2, =0xC0010007
spba_continue
str r1, [r0, #SPBA_PRR_OFFSET]
spba_check_loop
ldr r3, [r0, #SPBA_PRR_OFFSET]
cmp r2, r3
bne spba_check_loop
add r0, r0, #4
cmp r0, r4
ble spba_continue
; Configure CS4 so we can read PBC user switches
ldr r1, =CSP_BASE_REG_PA_WEIM
ldr r0, =0x0000D843
;ldr r0, =0x0000DCF6
str r0, [r1, #WEIM_CSCR4U_OFFSET]
ldr r0, =0x22252521
;ldr r0, =0x444A4541
str r0, [r1, #WEIM_CSCR4L_OFFSET]
ldr r0, =0x22220A00
;ldr r0, =0x44443302
str r0, [r1, #WEIM_CSCR4A_OFFSET]
; Enable IPU DI to get acknowledge for max_podf value change
ldr r1, =CSP_BASE_REG_PA_IPU
; IPU configuration register (IPU_CONF):
; DI_EN = Display interface enabled = (1 << 6) = 0x00000040
; ------------
; 0x00000040
ldr r0, =0x00000040
str r0, [r1]
IF NANDBOOT_DEBUG
;led0 & led1 off
ldr r0, =CSP_BASE_MEM_PA_CS4
ldr r1, =0x00c0
strh r1,[r0,#4]
ENDIF
;
; configure enhanced SDRAM/DDR contoller (ESDCTL) registers
;
esdctl_init
;
; Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
; in SW_PAD_CTL registers
;
; SDCLK
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x26C)
ldr r0, [r1]
bic r0, r0, #(1 << 12)
str r0, [r1]
; CAS
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x270)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; RAS
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x274)
ldr r0, [r1]
bic r0, r0, #(1 << 2)
str r0, [r1]
; CS2 (CSD0)
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x27C)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; DQM3
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x284)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x288)
ldr r2, =22 ; (0x2E0 - 0x288) / 4 = 22
pad_loop
ldr r0, [r1]
bic r0, r0, #(1 << 22)
bic r0, r0, #(1 << 12)
bic r0, r0, #(1 << 2)
str r0, [r1]
add r1, r1, #4
subs r2, r2, #0x1
bne pad_loop
;
; Configure enhanced SDRAM/DDR contoller (ESDCTL)
;
ldr r1, =CSP_BASE_REG_PA_ESDCTL
ldr r2, =CSP_BASE_MEM_PA_CSD0
; Configure SDRAM timing parameters
ldr r0, =0x006AC73A
str r0, [r1, #ESDCTL_ESDCFG0_OFFSET]
; Reset
ldr r0, =0x2
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Configure for DDR
ldr r0, =0x4
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Hold for more than 200ns
ldr r0, =0x10000
hold
subs r0, r0, #0x1
bne hold
; Set precharge command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Precharge command (1 << 28) = 0x10000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x92100000
ldr r0, =0x92100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Access SDRAM with A10 high to precharge all banks
ldr r0, =0x0
str r0, [r2, #0xF00]
; Set autorefresh command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Autorefresh command (2 << 28) = 0x20000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xA2100000
ldr r0, =0xA2100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Use writes to refresh all banks of SDRAM
ldr r0, =0x0
str r0, [r2]
str r0, [r2]
; Set load mode command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Load mode command (3 << 28) = 0x30000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xB2100000
ldr r0, =0xB2100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Use SDRAM write to load SDRAM mode register
ldr r0, =0x0
strb r0, [r2, #0x33] ; address used for mode, data ignored
ldr r3, =(CSP_BASE_MEM_PA_CSD0+0x01000000)
strb r0, [r3] ; address used for mode, data ignored
; Set load mode command
;
; PRCT - Precharge timer disabled (0 << 0) = 0x00000000
; BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080
; FP - No full page mode (0 << 8) = 0x00000000
; PWDT - Power down timeout 128 clocks (3 << 10) = 0x00000C00
; SREFR - 4 rows refreshed each clock (3 << 13) = 0x00006000
; DSIZ - 32-bit memory width (2 << 16) = 0x00020000
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Normal mode command (0 << 28) = 0x00000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x82226C80
ldr r0, =0x82226C80
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Configure misc SDRAM parameters
ldr r0, =0xC
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Increase hold time on DDR write delay lines
; ldr r0, =0x60000
; str r0, [r1, #ESDCTL_ESDDLY5_OFFSET]
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Configure the interrupt controller. Mask and clear any pending
; interrupts.
;--------------------------------------------------------------------------
mov r0, #0
ldr r1, =CSP_BASE_REG_PA_AVIC
str r0, [r1, #AVIC_INTENABLEH_OFFSET] ; disable all interrupt sources
str r0, [r1, #AVIC_INTENABLEL_OFFSET] ; disable all interrupt sources
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Set up the power management/monitoring registers. Set conditions during
; sleep modes.
;--------------------------------------------------------------------------
;
;none
;relocate IPL to DDR memory
ldr r1, =IPLRelocateSrc
ldr r0, =IPLRelocateDst
ldr r2, =(IPLRelocateSize/16)
10
ldmia r1!, {r3-r6}
stmia r0!, {r3-r6}
subs r2, r2, #1
bne %b10
20
adr r2, DDRRamStart
ldr r3, =(IPLRelocateSrc)
sub r3, r2, r3
ldr r4, =(IPLRelocateDst)
add r2, r4, r3
mov pc, r2
DDRRamStart
;now run in DDR memory
;setup Stack in DDR memory
ldr sp, =IPLStackEnd
;load and boot SPL
b NandBoot
;
; copy NFC buffer #0 into align 4 buffer
;
RdPage512Align4
stmfd sp!, {r1 - r11}
ldr r1, =g_pNFC
ldr r1, [r1]
mov r2, #512
rd512_align4
ldmia r1!, {r4 - r11}
stmia r0!, {r4 - r11}
subs r2, r2, #32
bne rd512_align4
ldmfd sp!, {r1 - r11}
mov pc, lr
;
; copy NFC buffer #0-#3 into align 4 buffer
;
RdPage2048Align4
stmfd sp!, {r1 - r11}
ldr r1, =g_pNFC
ldr r1, [r1]
mov r2, #2048
rd2048_align4
ldmia r1!, {r4 - r11}
stmia r0!, {r4 - r11}
subs r2, r2, #32
bne rd2048_align4
ldmfd sp!, {r1 - r11}
mov pc, lr
END
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