📄 startup.s
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;******************************************************************************
;*
;* Copyright (c) Microsoft Corporation. All rights reserved.
;*
;* Use of this source code is subject to the terms of the Microsoft end-user
;* license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;* If you did not accept the terms of the EULA, you are not authorized to use
;* this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;* install media.
;*
;******************************************************************************
;*
;* Copyright (C) 2006, Freescale Semiconductor, Inc. All Rights Reserved
;* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
;* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
;* FREESCALE SEMICONDUCTOR, INC.
;*
;******************************************************************************
;*
;* FILE: startup.s
;*
;* PURPOSE: Before control is transferred to the kernel, the boot loader
;* calls this StartUp code to put the CPU into an initialized state.
;*
;******************************************************************************
AREA Init, CODE, READONLY
INCLUDE mxarm11_base_regs.inc
INCLUDE mxarm11_base_mem.inc
INCLUDE mx31_base_regs.inc
INCLUDE mx31_base_mem.inc
INCLUDE constant.inc
IMPORT NandBoot
IMPORT g_pNFC
EXPORT RdPage512Align4
EXPORT RdPage2048Align4
GBLL NANDBOOT_DEBUG
NANDBOOT_DEBUG SETL {TRUE}
ENTRY ; Mark first instruction to execute
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Put the processor in supervisor mode
; Disable the interrupt request (IRQ) and fast interrupt request (FIQ)
; inputs
;--------------------------------------------------------------------------
StartUp
mrs r0, cpsr ; r0 = CPSR
mov r0, #ARM_CPSR_MODE_SVC ; enter supervisor mode
orr r0, r0, #ARM_CPSR_IRQDISABLE ; disable normal IRQ
orr r0, r0, #ARM_CPSR_FIQDISABLE ; disable fast IRQ
;orr r0, r0, #ARM_CPSR_PRECISE ; enable precise data aborts
msr cpsr_xc, r0 ; update CPSR control bits
;
; Configure auxiliary control register
;
mrc p15, 0, r0, c1, c0, 1 ; r0 = auxiliary control reg
;bic r0, r0, #ARM_AUXCR_DB ; disable dynamic branch pred
;bic r0, r0, #ARM_AUXCR_SB ; disable static branch pred
orr r0, r0, #ARM_AUXCR_HUM ; disable hit under miss (Errata 364296)
mcr p15, 0, r0, c1, c0, 1 ; update auxiliary control reg
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Disable memory management unit (MMU) and both the instruction and data
; caches
;--------------------------------------------------------------------------
mrc p15, 0, r0, c1, c0, 0 ; r0 = system control reg
bic r0, r0, #ARM_CTRL_ICACHE ; disable ICache
bic r0, r0, #ARM_CTRL_DCACHE ; disable DCache
bic r0, r0, #ARM_CTRL_MMU ; disable MMU
bic r0, r0, #ARM_CTRL_VECTORS ; set vector base to 0x00000000
orr r0, r0, #ARM_CTRL_FLOW ; program flow predicition enabled
orr r0, r0, #ARM_CTRL_FI ; enable low interrupt latency (Errata 364296)
mcr p15, 0, r0, c1, c0, 0 ; update system control reg
;
; Configure ARM Peripheral Port Memory Remap Register (PPMRR)
;
ldr r0, =ARM_PPMRR_CONFIG ; r0 = PPMRR configuration
mcr p15, 0, r0, c15, c2, 4 ; update PPMRR
;
; Disable L2 cache
;
ldr r1, =CSP_BASE_REG_PA_L2CC
ldr r0, =0x0
str r0, [r1, #L2CC_CR_OFFSET]
;
; Configure ARM coprocessor access control register
;
ldr r0, =ARM_CACR_CONFIG ; r0 = CACR configuration
mcr p15, 0, r0, c1, c0, 2 ; update CACR
;
; configure AHB<->IP-bus interface (AIPS) registers
;
ldr r1, =CSP_BASE_REG_PA_AIPSAREG
ldr r2, =CSP_BASE_REG_PA_AIPSBREG
; except for AIPS regs, configure all peripherals as follows:
; unbuffered writes (BW=0)
; disable supervisor protect (SP=0)
; disable write protect (WP=0)
; disable trusted protect (TP=0)
mov r0, #0
str r0, [r1, #AIPSREG_PACR1_OFFSET]
str r0, [r1, #AIPSREG_PACR2_OFFSET]
str r0, [r1, #AIPSREG_PACR3_OFFSET]
str r0, [r1, #AIPSREG_OPACR0_OFFSET]
str r0, [r1, #AIPSREG_OPACR1_OFFSET]
str r0, [r1, #AIPSREG_OPACR2_OFFSET]
str r0, [r1, #AIPSREG_OPACR3_OFFSET]
str r0, [r1, #AIPSREG_OPACR4_OFFSET]
str r0, [r2, #AIPSREG_PACR1_OFFSET]
str r0, [r2, #AIPSREG_PACR2_OFFSET]
str r0, [r2, #AIPSREG_PACR3_OFFSET]
str r0, [r2, #AIPSREG_OPACR0_OFFSET]
str r0, [r2, #AIPSREG_OPACR1_OFFSET]
str r0, [r2, #AIPSREG_OPACR2_OFFSET]
str r0, [r2, #AIPSREG_OPACR3_OFFSET]
str r0, [r2, #AIPSREG_OPACR4_OFFSET]
; AIPS regs (PACR0) are configured as follows:
; unbuffered writes (BW=0)
; enable supervisor protect (SP=1)
; disable write protect (WP=0)
; disable trusted protect (TP=0)
orr r0, r0, #(1 << (28+2))
str r0, [r1, #AIPSREG_PACR0_OFFSET]
str r0, [r2, #AIPSREG_PACR0_OFFSET]
; Set all MPRx to be non-bufferable, trusted for R/W,
; not forced to user-mode.
ldr r0, =(0x77777777)
str r0, [r1, #AIPSREG_MPR0_OFFSET]
str r0, [r1, #AIPSREG_MPR1_OFFSET]
str r0, [r2, #AIPSREG_MPR0_OFFSET]
str r0, [r2, #AIPSREG_MPR1_OFFSET]
; set up system clocks
;
ldr r1, =CSP_BASE_REG_PA_CCM
; Control register (CCMR):
; FPME = FPM enabled = (1 << 0) = 0x00000001
; PRCS = CKIL is PLL ref = (2 << 1) = 0x00000002
; MPE = MCU PLL enabled = (1 << 3) = 0x00000008
; SBYCS = Enabled in standby = (1 << 4) = 0x00000010
; ROMW = All masters 1 WS = (3 << 5) = 0x00000060
; MDS = MCU PLL is source = (0 << 7) = 0x00000000
; SPE = serial PLL enabled = (1 << 8) = 0x00000100
; UPE = USB PLL enabled = (1 << 9) = 0x00000200
; WAMO = masked all but DSM = (0 << 10) = 0x00000000
; FIRS = FIRI source usb_clk = (1 << 11) = 0x00000800
; LPM = wait mode = (0 << 14) = 0x00000000
; RAMW = All masters 1 WS = (3 << 16) = 0x00030000
; SSI1S = SSI1 source serial_clk = (2 << 18) = 0x00080000
; SSI1S = SSI2 source serial_clk = (2 << 21) = 0x00400000
; PERCS = per_clk source ipg_clk = (1 << 24) = 0x01000000
; CSCS = CSI source SRPLL = (1 << 25) = 0x02000000
; FPMF = FPM factor 1024 = (1 << 26) = 0x04000000
; WBEN = well bias disabled = (0 << 27) = 0x00000000
; VSTBY = no standby = (0 << 28) = 0x00000000
; L2PG = no L2 power gating (0 << 29) = 0x00000000
; ------------
; 0x074B0B7B
ldr r0, =0x074B0B7B
str r0, [r1, #CCM_CCMR_OFFSET]
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 532 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 266 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 133 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 4 = 133 MHz
; IPG_CLK = HCLK / 2 = 66.5 MHz
; NFC_CLK = HCLK / 6 = 22.167 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /1 = (1 << 0) = 0x00000001
; MAX_PODF = /4 = (3 << 3) = 0x00000018
; IPG_PODF = /2 = (1 << 6) = 0x00000040
; NFC_PODF = /6 = (5 << 8) = 0x00000500
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831D59
ldr r0, =0xFF831D59
str r0, [r1, #CCM_PDR0_OFFSET]
; MCU PLL control (MPCTL)
;
; MCU_CLK = (CKIL)*FPM * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (32768)*1024 * 2 * (7 + 51/(54+1)) / (0+1)
; = 531990267 MHz
;
; MFN = 51 = (51 << 0) = 0x00000033
; MFI = 7 = (7 << 10) = 0x00001C00
; MFD = 54 = (54 << 16) = 0x00360000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x00361C33
ldr r0, =0x00361C33
str r0, [r1, #CCM_MPCTL_OFFSET]
; configure AHB crossbar switch (MAX) registers
;
ldr r1, =CSP_BASE_REG_PA_MAX
; Master Priority (0 = highest priority)
; M4 > M2 > M3 > M5 > M0 > M1
; DMA > PAHB > RTIC > USB > L2M0 > L2M1
ldr r0, =(0x00302154)
; Master priority configured the same for all slaves
str r0, [r1, #MAX_MPR0_OFFSET]
str r0, [r1, #MAX_MPR1_OFFSET]
str r0, [r1, #MAX_MPR2_OFFSET]
str r0, [r1, #MAX_MPR3_OFFSET]
str r0, [r1, #MAX_MPR4_OFFSET]
; Slave control
; PARK - Ignored since PCTL not (0 << 0)
; PCTL - Park on last master (1 << 4)
; ARB - Fixed priority (0 << 8)
; HPE - High priority input disabled (0 << 16)
; HLP - Halt request has lowest priority (0 << 30)
; RO - Slave port registers can be written (0 << 31)
ldr r0, =(1 << 4)
; Slave control configured the same for all slaves
str r0, [r1, #MAX_SGPCR0_OFFSET]
str r0, [r1, #MAX_SGPCR1_OFFSET]
str r0, [r1, #MAX_SGPCR2_OFFSET]
str r0, [r1, #MAX_SGPCR3_OFFSET]
str r0, [r1, #MAX_SGPCR4_OFFSET]
; Master control
; AULB - Arbitration any time during undefined burst length (1 << 0)
ldr r0, =(1 << 0)
str r0, [r1, #MAX_MGPCR0_OFFSET]
str r0, [r1, #MAX_MGPCR1_OFFSET]
str r0, [r1, #MAX_MGPCR2_OFFSET]
str r0, [r1, #MAX_MGPCR3_OFFSET]
str r0, [r1, #MAX_MGPCR4_OFFSET]
str r0, [r1, #MAX_MGPCR5_OFFSET]
;
; configure multi-master memory interface (M3IF) registers
;
ldr r1, =CSP_BASE_REG_PA_M3IF
; M3IF Control Register (M3IFCTL)
; MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
; MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
; MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
; MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
; MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
; MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
; MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
; MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
; ------------
; 0x00000040
;
ldr r0, =0x00000040
str r0, [r1, #M3IF_M3IFCTL_OFFSET]
; *** SPBA Bus Init ***
ldr r0, =CSP_BASE_REG_PA_SPBA
add r4, r0, #(SPBA_NUM_SHARED_PERIPH * 4)
; Peripheral rights (write value)
; RAR0 = ARM has access (1 << 0)
; RAR1 = DSP has access (1 << 1)
; RAR2 = DMA has access (1 << 2)
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